公开(公告)号：US09181084B2

公开(公告)日：2015-11-10

申请号：US12652715

申请日：2010-01-05

Applicant: Chien-Hung Liu

Inventor： Chien-Hung Liu

IPC: H01L23/02 ,  B81C1/00 ,  H01L21/683 ,  H01L23/00

CPC classification number: B81C1/00325 ,  B81B2207/092 ,  B81B2207/097 ,  B81C1/00301 ,  B81C2201/0115 ,  B81C2203/0118 ,  H01L21/6835 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/93 ,  H01L2221/68304 ,  H01L2221/68331 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2221/68386 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/11009 ,  H01L2224/11019 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/93 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15788 ,  H01L2224/0231 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2924/00

Abstract: The invention provides an electronic device package and fabrication method thereof. The electronic device package includes a sensor chip. An upper surface of the sensor chip comprises a sensing film. A covering plate having an opening structure covers the upper surface of the sensor chip. A cavity is between the covering plate and the sensor chip, corresponding to a position of the sensing film, where the cavity communicates with the opening structure. A spacer is between the covering plate and the sensor chip, surrounding the cavity. A pressure releasing region is between the spacer and the sensing film.

Abstract translation: 本发明提供一种电子器件封装及其制造方法。 电子装置封装包括传感器芯片。 传感器芯片的上表面包括感测膜。 具有开口结构的覆盖板覆盖传感器芯片的上表面。 覆盖板和传感器芯片之间的腔体对应于感测膜的位置，其中空腔与开口结构连通。 间隔件位于覆盖板和传感器芯片之间，围绕腔体。 压力释放区域位于间隔件和感测膜之间。

公开(公告)号：US08748949B2

公开(公告)日：2014-06-10

申请号：US12940607

申请日：2010-11-05

Applicant: Chien-Hung Liu ,  Cheng-Te Chou

Inventor： Chien-Hung Liu ,  Cheng-Te Chou

IPC: H01L23/48 ,  H01L21/70 ,  H01L29/40

CPC classification number: H01L27/14618 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/93 ,  H01L24/94 ,  H01L25/0657 ,  H01L27/14683 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/051 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/05638 ,  H01L2224/05688 ,  H01L2224/13022 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32052 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/01014 ,  H01L2924/053 ,  H01L2924/01 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions.

Abstract translation: 本发明提供一种芯片封装及其制造方法。 在一个实施例中，芯片封装包括：具有相对的第一和第二表面，至少一个焊盘区域和至少一个器件区域的半导体衬底; 多个导电焊盘结构，设置在半导体衬底的第一表面处的焊盘区域上; 多个彼此隔离的重掺杂区域，其下面并电连接到导电焊盘结构; 以及在重掺杂区域下面的多个导电凸块，并通过重掺杂区域电连接到导电焊盘结构。

公开(公告)号：US08614488B2

公开(公告)日：2013-12-24

申请号：US13314114

申请日：2011-12-07

Applicant: Ying-Nan Wen ,  Ho-Yin Yiu ,  Yen-Shih Ho ,  Shu-Ming Chang ,  Chien-Hung Liu ,  Shih-Yi Lee ,  Wei-Chung Yang

Inventor： Ying-Nan Wen ,  Ho-Yin Yiu ,  Yen-Shih Ho ,  Shu-Ming Chang ,  Chien-Hung Liu ,  Shih-Yi Lee ,  Wei-Chung Yang

IPC: H01L21/70

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2224/02372 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05672 ,  H01L2224/11002 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A chip package includes: a substrate; a drain and a source regions located in the substrate; a gate located on or buried in the substrate; a drain conducting structure, a source conducting structure, and a gate conducting structure, disposed on the substrate and electrically connected to the drain region, the source region, and the gate, respectively; a second substrate disposed beside the substrate; a second drain and a second source region located in the second substrate, wherein the second drain region is electrically connected to the source region; a second gate located on or buried in the second substrate; and a second source and a second gate conducting structure disposed on the second substrate and electrically connected to the second source region and the second gate, respectively, wherein terminal points of the drain, the source, the gate, the second source, and the second gate conducting structures are substantially coplanar.

Abstract translation: 芯片封装包括：基板; 位于衬底中的漏极和源极区域; 位于衬底上或埋在衬底中的门; 漏极导电结构，源极导电结构和栅极导电结构，分别设置在所述衬底上并电连接到所述漏极区域，所述源极区域和所述栅极; 设置在所述基板旁边的第二基板; 位于所述第二基板中的第二漏极和第二源极区域，其中所述第二漏极区域电连接到所述源极区域; 位于第二基板上或埋在第二基板中的第二栅极; 以及第二源极和第二栅极导电结构，其设置在所述第二基板上并分别电连接到所述第二源极区域和所述第二栅极，其中所述漏极，所述源极，所述栅极，所述第二源极和所述第二栅极的端点 栅极导电结构基本上共面。

公开(公告)号：US08362515B2

公开(公告)日：2013-01-29

申请号：US13081346

申请日：2011-04-06

Applicant: Chia-Ming Cheng ,  Chien-Hung Liu

Inventor： Chia-Ming Cheng ,  Chien-Hung Liu

IPC: H01L33/00

CPC classification number: H01L23/49805 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/481 ,  H01L23/50 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2924/0002 ,  H01L2924/01021 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the invention provides a chip package which includes a substrate having an upper surface and a lower surface and having at least a side surface, and at least a trench extending from the upper surface towards the lower surface and extending from the side surface towards an inner portion of the substrate, wherein a width of the trench near the upper surface is not equal to a width of the trench near the lower surface, and at least an insulating layer located on a sidewall of the trench, and at least a conducting pattern located on the insulating layer, wherein the side surface is separated from the conducting pattern in the trench by a predetermined distance such that a portion of the insulating layer is exposed, and at least a conducting region electrically connected to the conducting pattern.

Abstract translation: 本发明的一个实施例提供了一种芯片封装，其包括具有上表面和下表面的基板，并且至少具有一个侧表面，以及至少一个从上表面向下表面延伸并且从侧表面向着 衬底的内部部分，其中靠近上表面的沟槽的宽度不等于下表面附近的沟槽的宽度，以及至少位于沟槽的侧壁上的绝缘层，并且至少导电 位于所述绝缘层上，其中所述侧表面与所述沟槽中的导电图案分离预定距离，使得所述绝缘层的一部分露出，以及至少导电区域电连接到所述导电图案。

公开(公告)号：US20120274870A1

公开(公告)日：2012-11-01

申请号：US13549798

申请日：2012-07-16

Applicant: Chien-Hung Liu

Inventor： Chien-Hung Liu

IPC: G02F1/1343

CPC classification number: G02F1/136259 ,  G02F2001/136263

Abstract: One aspect of the present disclosure relates to a common repair structure for repairing scanning and/or data line defects in a liquid crystal display panel. In one embodiment, the common repair structure includes a plurality of “H” shaped structures, where each “H” shaped structure is placed over a corresponding segment of two neighboring scanning lines located between and associated with two neighboring pixels along the second direction or a corresponding segment of two neighboring data lines located between and associated with two neighboring pixels along the first direction.

Abstract translation: 本公开的一个方面涉及用于修复液晶显示面板中的扫描和/或数据线缺陷的常见修复结构。 在一个实施例中，公共修复结构包括多个H形结构，其中每个H形结构放置在沿着第二方向位于两个相邻像素之间并且与两个相邻像素相关联的两个相邻扫描线的对应段上，或者相应的二段 位于沿与第一方向相邻的两个相邻像素之间并与之相关联的相邻数据线。

公开(公告)号：US08264631B2

公开(公告)日：2012-09-11

申请号：US12616420

申请日：2009-11-11

Applicant: Chien-Hung Liu

Inventor： Chien-Hung Liu

IPC: G02F1/1333

CPC classification number: G02F1/136259 ,  G02F2001/136263

Abstract: One aspect of the present disclosure relates to a common repair structure for repairing scanning and/or data line defects in a liquid crystal display panel. In one embodiment, the common repair structure includes a plurality of “H” shaped structures, where each “H” shaped structure is placed over a corresponding segment of two neighboring scanning lines located between and associated with two neighboring pixels along the second direction or a corresponding segment of two neighboring data lines located between and associated with two neighboring pixels along the first direction.

Abstract translation: 本公开的一个方面涉及用于修复液晶显示面板中的扫描和/或数据线缺陷的常见修复结构。 在一个实施例中，公共修复结构包括多个“H”形结构，其中每个“H”形结构被放置在沿着第二方向位于两个相邻像素之间并与之相关联的两个相邻扫描线的对应段上，或者 两个相邻数据线的对应段位于沿着第一方向的两个相邻像素之间并与之相关联。

公开(公告)号：US08263877B2

公开(公告)日：2012-09-11

申请号：US12837487

申请日：2010-07-15

Applicant: Chien-Hung Liu ,  Po-Chuan Hsieh ,  Yu-Chang Pai ,  Shou-Kuo Hsu

Inventor： Chien-Hung Liu ,  Po-Chuan Hsieh ,  Yu-Chang Pai ,  Shou-Kuo Hsu

IPC: H05K1/11

CPC classification number: H05K1/162 ,  H05K1/0239 ,  H05K2201/0397 ,  H05K2201/10015 ,  H05K2201/1034

Abstract: A printed circuit board includes a first signal layer, a second signal layer, and a dielectric layer sandwiched between the first signal layer and the second signal layer. The first signal layer includes two pads. The second signal layer includes two conducting pieces connected to two signal traces. The shape and material of the pads are the same as the shape and material of the conducting pieces. The projections of the pads on the second signal layer are overlapping with the conducting pieces.

Abstract translation: 印刷电路板包括第一信号层，第二信号层和夹在第一信号层和第二信号层之间的电介质层。 第一信号层包括两个焊盘。 第二信号层包括连接到两个信号迹线的两个导电片。 垫的形状和材料与导电片的形状和材料相同。 第二信号层上的焊盘的突起与导电片重叠。

公开(公告)号：US20120156320A1

公开(公告)日：2012-06-21

申请号：US12971466

申请日：2010-12-17

Applicant: Wen-Yuh Jywe ,  Jing-Chung Shen ,  Chin-Tien Yang ,  Chien-Hung Liu ,  Jau-Jiu Ju ,  Chia-Hung Wu ,  Chun-Chieh Huang ,  Lili Duan ,  Yuan-Chin Lee

Inventor： Wen-Yuh Jywe ,  Jing-Chung Shen ,  Chin-Tien Yang ,  Chien-Hung Liu ,  Jau-Jiu Ju ,  Chia-Hung Wu ,  Chun-Chieh Huang ,  Lili Duan ,  Yuan-Chin Lee

IPC: B29C59/16 ,  B29C37/00

CPC classification number: B23K26/0853

Abstract: A manufacturing-process equipment has a platform assembly, a measurement feedback assembly and a laser-working assembly. The platform assembly has a base and a hybrid-moving platform. The base has a mounting frame. The hybrid-moving platform is mounted on the base and has a long-stroke moving stage and a piezo-driven micro-stage. The long-stroke moving stage has a benchmark set and a driving device. The piezo-driven micro-stage is connected to the long-stroke moving stage and has a working platform. The measurement feedback assembly is securely mounted on the platform assembly and has a laser interferometer, a reflecting device and a signal-receiving device. The laser-working assembly is mounted on the platform assembly, is electrically connected to the measurement feedback assembly and has a laser direct-writing head, a controlling interface device and a positioning interface device.

Abstract translation: 制造过程设备具有平台组件，测量反馈组件和激光加工组件。 平台组件具有基座和混合动力平台。 底座有一个安装架。 混合动力平台安装在基座上，具有长行程移动台和压电驱动微型平台。 长冲程移动台具有基准组和驱动装置。 压电驱动微型平台连接到长行程移动台，并具有工作平台。 测量反馈组件牢固地安装在平台组件上，并具有激光干涉仪，反射装置和信号接收装置。 激光加工组件安装在平台组件上，电连接到测量反馈组件，并具有激光直写头，控制接口装置和定位接口装置。

公开(公告)号：US20110233782A1

公开(公告)日：2011-09-29

申请号：US13052769

申请日：2011-03-21

Applicant: Shu-Ming CHANG ,  Bai-Yao Lou ,  Ying-Nan Wen ,  Chien-Hung Liu

Inventor： Shu-Ming CHANG ,  Bai-Yao Lou ,  Ying-Nan Wen ,  Chien-Hung Liu

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L21/50 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/92 ,  H01L24/93 ,  H01L24/94 ,  H01L33/62 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/03825 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/119 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/32052 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/92142 ,  H01L2224/92143 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/0231 ,  H01L2224/11 ,  H01L2224/1182 ,  H01L2224/03 ,  H01L2224/0382 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.

Abstract translation: 公开了一种电子器件封装。 该封装包括至少一个具有第一表面和与其相对的第二表面的半导体芯片，其中至少一个再分配层设置在半导体芯片的第一表面上并与至少一个导电焊盘结构电连接。 至少一个邻接部分设置在再分布层上并与其电接触。 钝化层覆盖半导体芯片的第一表面并围绕邻接部分。 将衬底附着到半导体芯片的第二表面上。 还公开了一种电子器件封装的制造方法。

公开(公告)号：US07981727B2

公开(公告)日：2011-07-19

申请号：US11987232

申请日：2007-11-28

Applicant: Chien-Hung Liu ,  Sih-Dian Lee

Inventor： Chien-Hung Liu ,  Sih-Dian Lee

IPC: H01L21/00

CPC classification number: H01L31/0203 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/13 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14687 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/00

Abstract: Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A first trench is formed by etching the semiconductor exposing an inter-layered dielectric layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the first trench is removed to create a second trench. The insulating layer and the ILD layer are sequentially removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an S-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.

Abstract translation: 电子装置晶圆级规包装及其制造方法。 提供了形成有多个电子器件的半导体晶片。 半导体晶片与支撑基板结合。 半导体衬底的背面变薄。 通过蚀刻暴露层间电介质层的半导体形成第一沟槽。 绝缘层顺应地沉积在半导体衬底的背面上。 去除第一沟槽底部的绝缘层以产生第二沟槽。 依次去除绝缘层和ILD层，暴露一对接触焊盘的一部分。 导电层顺应地形成在半导体的背面上。 导电层被图案化之后，导电层和接触垫构成S形连接。 接下来，随后形成外部连接和端子接触焊盘。