发明申请
US20080191746A1 AUTOMATIC STATIC PHASE ERROR AND JITTER COMPENSATION IN PLL CIRCUITS
有权
PLL电路中的自动静态相位误差和抖动补偿
- 专利标题: AUTOMATIC STATIC PHASE ERROR AND JITTER COMPENSATION IN PLL CIRCUITS
- 专利标题(中): PLL电路中的自动静态相位误差和抖动补偿
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申请号: US11672737申请日: 2007-02-08
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公开(公告)号: US20080191746A1公开(公告)日: 2008-08-14
- 发明人: DANIEL J. FRIEDMAN , Yong Liu , Woogeun Rhee
- 申请人: DANIEL J. FRIEDMAN , Yong Liu , Woogeun Rhee
- 主分类号: H03L7/087
- IPC分类号: H03L7/087 ; H03L7/085 ; H03D13/00
摘要:
An instantaneous phase error detector (IPED) and method includes a first gate configured to logically OR output phase error signals as data to a first latch, and a second gate configured to logically combine the output phase error signals to clock the first latch. A delay element delays to the data to the first latch where the output of the first latch provides instantaneous phase error change information. A second latch is coupled to the output phase error signals to output a lead/lag signal to indicate which of the output phase error signals is leading. A phase-locked loop employing the output of the IPED is also disclosed along with static phase measurement and jitter optimization features.