发明申请
US20080191746A1 AUTOMATIC STATIC PHASE ERROR AND JITTER COMPENSATION IN PLL CIRCUITS 有权
PLL电路中的自动静态相位误差和抖动补偿

AUTOMATIC STATIC PHASE ERROR AND JITTER COMPENSATION IN PLL CIRCUITS
摘要:
An instantaneous phase error detector (IPED) and method includes a first gate configured to logically OR output phase error signals as data to a first latch, and a second gate configured to logically combine the output phase error signals to clock the first latch. A delay element delays to the data to the first latch where the output of the first latch provides instantaneous phase error change information. A second latch is coupled to the output phase error signals to output a lead/lag signal to indicate which of the output phase error signals is leading. A phase-locked loop employing the output of the IPED is also disclosed along with static phase measurement and jitter optimization features.
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