发明申请
- 专利标题： Addressing Strategy for Viterbi Metric Computation
- 专利标题（中）： 维特比计量计算的解决策略
-
申请号： US11630653申请日： 2005-06-20
-
公开(公告)号： US20080192865A1公开(公告)日： 2008-08-14
- 发明人: Christine Schenone , Layachi Daineche , Aritz Sanchez Lekue
- 申请人： Christine Schenone , Layachi Daineche , Aritz Sanchez Lekue
- 申请人地址： NL Eindhoven
- 专利权人： Koninklijke Philips Electronics N.V.
- 当前专利权人： Koninklijke Philips Electronics N.V.
- 当前专利权人地址： NL Eindhoven
- 优先权： EP04300395.3 20040623
- 国际申请： PCT/IB2005/052019 WO 20050620
- 主分类号： H03D1/00
- IPC分类号： H03D1/00 ; H04L27/06 ; H03M5/00 ; H03M13/41
摘要：
The present invention relates to an addressing architecture for parallel processing of recursive data. A basic idea of the present invention is to store a calculated new path metric at the memory location used by the old path metric, which old metric was employed to calculate the new metric. If m metric values are read and m metric values are simultaneously calculated in parallel, it is possible to store the new, calculated metrics in the memory position where the old metrics were held. The present invention is advantageous, since the size of the storage area for the path metrics is reduced to half compared to the storage area employed in prior art Viterbi decoders for the same performance with regard to path metric computations.
公开/授权文献
- US07818654B2 Addressing strategy for Viterbi metric computation 公开/授权日：2010-10-19
信息查询
IPC分类:
