公开(公告)号：US07818654B2

公开(公告)日：2010-10-19

申请号：US11630653

申请日：2005-06-20

申请人： Christine Schenone ,  Layachi Daineche ,  Aritz Sanchez Lekue

发明人： Christine Schenone ,  Layachi Daineche ,  Aritz Sanchez Lekue

IPC分类号： H03M13/03

CPC分类号： H03M13/4107 ,  H03M13/6505

摘要： There is provided an addressing architecture for parallel processing of recursive data. A basic idea is to store a calculated new path metric at the memory location used by the old path metric, which old metric was employed to calculate the new metric. If m metric values are read and m metric values are simultaneously calculated in parallel, it is possible to store the new, calculated metrics in the memory position where the old metrics were held. This is advantageous, since the size of the storage area for the path metrics is reduced to half compared to the storage area employed in prior art Viterbi decoders for the same performance with regard to path metric computations.

摘要翻译： 提供了一种用于并行处理递归数据的寻址架构。 一个基本思想是将计算的新路径度量存储在由旧路径度量使用的存储位置，该路径度量用于计算新度量。 如果读取m个度量值并且同时并行计算m个度量值，则可以将新的计算的度量存储在保持旧度量的存储器位置。 这是有利的，因为用于相对于路径度量计算的相同性能的现有技术的维特比解码器中使用的用于路径量度的存储区域的尺寸减小到一半。

公开(公告)号：US20080192865A1

公开(公告)日：2008-08-14

申请号：US11630653

申请日：2005-06-20

申请人： Christine Schenone ,  Layachi Daineche ,  Aritz Sanchez Lekue

发明人： Christine Schenone ,  Layachi Daineche ,  Aritz Sanchez Lekue

IPC分类号： H03D1/00 ,  H04L27/06 ,  H03M5/00 ,  H03M13/41

CPC分类号： H03M13/4107 ,  H03M13/6505

摘要： The present invention relates to an addressing architecture for parallel processing of recursive data. A basic idea of the present invention is to store a calculated new path metric at the memory location used by the old path metric, which old metric was employed to calculate the new metric. If m metric values are read and m metric values are simultaneously calculated in parallel, it is possible to store the new, calculated metrics in the memory position where the old metrics were held. The present invention is advantageous, since the size of the storage area for the path metrics is reduced to half compared to the storage area employed in prior art Viterbi decoders for the same performance with regard to path metric computations.

摘要翻译： 本发明涉及用于并行处理递归数据的寻址架构。 本发明的基本思想是将计算出的新路径度量存储在由旧路径度量使用的存储位置处，该旧路径量度用于计算新度量。 如果读取m个度量值并且同时并行计算m个度量值，则可以将新的计算的度量存储在保持旧度量的存储器位置。 本发明是有利的，因为用于相对于路径度量计算的相同性能的路径度量的存储区域的尺寸比现有技术的维特比解码器中使用的存储区域减小了一半。