发明申请
- 专利标题: SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
- 专利标题(中): 半导体器件及其制造方法
-
申请号: US12029478申请日: 2008-02-12
-
公开(公告)号: US20080197381A1公开(公告)日: 2008-08-21
- 发明人: Yoshiya Kawashima , Yoshinao Miura , Hitoshi Ninomiya
- 申请人: Yoshiya Kawashima , Yoshinao Miura , Hitoshi Ninomiya
- 申请人地址: JP KAWASAKI
- 专利权人: NEC ELECTRONICS CORPORATION
- 当前专利权人: NEC ELECTRONICS CORPORATION
- 当前专利权人地址: JP KAWASAKI
- 优先权: JP2007-35044 20070215; JP2007-168551 20070627
- 主分类号: H01L29/04
- IPC分类号: H01L29/04 ; H01L21/336
摘要:
A semiconductor device is provided with a vertical MOSFET including an N-type drift region that has a {110} crystal plane serving as the main surface thereof, a trench gate structure formed in a trench that has a {100} crystal plane serving as a sidewall surface thereof, and plural P-type column region structures provided in the N-type drift region 3, making up the super-junction structure. The P-type column region structures are disposed so as to be separated from each other in a plan view, and each of the plurality of column structures includes a plurality of column regions of the second conductivity type separated from each other in a cross-sectional view. By applying ion implantation of a P-type dopant to the main surface from a direction vertical to the main surface, the P-type column regions are formed down to sufficiently deeper positions in the drift region due to channeling. By so doing, it is possible to obtain a semiconductor device with an enhanced breakdown voltage. Further, since it is possible that a crystal plane of a channel is the {100} crystal plane, enabling a maximum electron mobility to be obtained, it is possible to increase on-current, so that on-resistance can be reduced.
信息查询
IPC分类: