公开(公告)号：US07829417B2

公开(公告)日：2010-11-09

申请号：US12128865

申请日：2008-05-29

申请人： Hitoshi Ninomiya ,  Yoshinao Miura ,  Yoshiya Kawashima

发明人： Hitoshi Ninomiya ,  Yoshinao Miura ,  Yoshiya Kawashima

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/266 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66734

摘要： A semiconductor apparatus with a superjunction structure includes a gate electrode which fills a trench that is formed in an epitaxial layer, and a column region which is surrounded by the gate electrode in a plane view. A photomask for forming the column region is elaborated. The photomask has a compensation pattern that compensates a deformation of a photo resist pattern caused by photo interference and a deformation of the ion implantation region diffused by heat treatment. Therefore extending direction of the gate electrode and the outer edge of the column region are substantially parallel.

摘要翻译： 具有超结构结构的半导体装置包括填充形成在外延层中的沟槽的栅极电极和在平面图中被栅电极包围的列区域。 阐述了用于形成柱区域的光掩模。 光掩模具有补偿图案，其补偿由光干涉引起的光致抗蚀剂图案的变形和通过热处理扩散的离子注入区域的变形。 因此，栅电极和列区域的外边缘的延伸方向基本上平行。

公开(公告)号：US20080197381A1

公开(公告)日：2008-08-21

申请号：US12029478

申请日：2008-02-12

申请人： Yoshiya Kawashima ,  Yoshinao Miura ,  Hitoshi Ninomiya

发明人： Yoshiya Kawashima ,  Yoshinao Miura ,  Hitoshi Ninomiya

IPC分类号： H01L29/04 ,  H01L21/336

CPC分类号： H01L29/7397 ,  H01L29/66348

摘要： A semiconductor device is provided with a vertical MOSFET including an N-type drift region that has a {110} crystal plane serving as the main surface thereof, a trench gate structure formed in a trench that has a {100} crystal plane serving as a sidewall surface thereof, and plural P-type column region structures provided in the N-type drift region 3, making up the super-junction structure. The P-type column region structures are disposed so as to be separated from each other in a plan view, and each of the plurality of column structures includes a plurality of column regions of the second conductivity type separated from each other in a cross-sectional view. By applying ion implantation of a P-type dopant to the main surface from a direction vertical to the main surface, the P-type column regions are formed down to sufficiently deeper positions in the drift region due to channeling. By so doing, it is possible to obtain a semiconductor device with an enhanced breakdown voltage. Further, since it is possible that a crystal plane of a channel is the {100} crystal plane, enabling a maximum electron mobility to be obtained, it is possible to increase on-current, so that on-resistance can be reduced.

摘要翻译： 半导体器件设置有包括具有{110}晶面用作其主表面的N型漂移区的垂直MOSFET，在具有{100}晶面的沟槽中形成的沟槽栅结构，作为 以及设置在N型漂移区域3中的多个P型列区域结构，构成超结结构。 P型列区域结构被布置成在平面图中彼此分离，并且多个列结构中的每一个都包括在横截面中彼此分离的多个第二导电类型的列区域 视图。 通过从垂直于主表面的方向向主表面施加P型掺杂剂的离子注入，P型列区域由于引导而形成在漂移区域中的足够深的位置。 通过这样做，可以获得具有增强的击穿电压的半导体器件。 此外，由于通道的晶面可以是{100}晶面，因此能够获得最大的电子迁移率，可以增加导通电流，从而可以降低导通电阻。

公开(公告)号：US07919374B2

公开(公告)日：2011-04-05

申请号：US12503297

申请日：2009-07-15

申请人： Hitoshi Ninomiya ,  Yoshinao Miura

发明人： Hitoshi Ninomiya ,  Yoshinao Miura

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/7808 ,  H01L29/7813

摘要： A conventional power MOSFET structure is difficult to improve a breakdown voltage of an element even using a super-junction structure. A power MOSFET according to an embodiment of the invention is a semiconductor device of a super-junction structure, including: a gate electrode filled in a trench formed on a semiconductor substrate; a gate wiring metal forming a surface layer; and a gate electrode plug connecting between the gate electrode and the gate wiring metal. Thus, a polysilicon layer necessary for the conventional typical power MOSFET is unnecessary. That is, column regions of an element active portion and an outer peripheral portion can be formed under the same conditions. As a result, it is possible to improve an element breakdown voltage as compared with the conventional one.

摘要翻译： 常规的功率MOSFET结构即使使用超结结构也难以提高元件的击穿电压。 根据本发明的实施例的功率MOSFET是超结结构的半导体器件，包括：填充在形成在半导体衬底上的沟槽中的栅电极; 形成表面层的栅极布线金属; 以及连接在栅极电极和栅极配线金属之间的栅电极插头。 因此，传统典型功率MOSFET所需的多晶硅层是不必要的。 也就是说，可以在相同条件下形成元件活性部分和外周部分的列区域。 结果，与现有技术相比，可以提高元件击穿电压。

公开(公告)号：US08035158B2

公开(公告)日：2011-10-11

申请号：US12110966

申请日：2008-04-28

申请人： Yoshinao Miura ,  Hitoshi Ninomiya

发明人： Yoshinao Miura ,  Hitoshi Ninomiya

IPC分类号： H01L29/66

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66734 ,  H01L29/7813

摘要： Aiming at realizing high breakdown voltage and low ON resistance of a semiconductor device having the super-junction structure, the semiconductor device of the present invention has a semiconductor substrate having an element forming region having a gate electrode formed therein, and a periphery region formed around the element forming region, and having an field oxide film formed therein; and a parallel p-n layer having n-type drift regions and p-type column regions alternately arranged therein, formed along the main surface of the semiconductor substrate, as being distributed over the element forming region and a part of the periphery region, wherein the periphery region has no column region formed beneath the end portion on the element forming region side of the field oxide film and has p-type column regions as at least one column region formed under the field oxide film.

摘要翻译： 为了实现具有超结结构的半导体器件的高击穿电压和低导通电阻，本发明的半导体器件具有半导体衬底，其具有形成有栅电极的元件形成区域和形成在其周围的周边区域 元件形成区域，并且其中形成有场氧化物膜; 以及沿半导体基板的主表面形成有n型漂移区和交替配置的p型列区的并行pn层，分布在元件形成区域和周边区域的一部分上，其中， 区域在场氧化膜的元件形成区域侧的端部之下没有形成列区域，并且具有作为在场氧化膜下形成的至少一个列区域的p型列区域。

公开(公告)号：US07538388B2

公开(公告)日：2009-05-26

申请号：US11483738

申请日：2006-07-11

申请人： Yoshinao Miura ,  Hitoshi Ninomiya

发明人： Yoshinao Miura ,  Hitoshi Ninomiya

IPC分类号： H01L23/62

CPC分类号： H01L29/0692 ,  H01L29/0634 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor substrate, and a parallel p-n layer provided between the main surface and the back surface of the semiconductor substrate, and first-conductivity-type drift region and second-conductivity-type partition regions alternately arranged therein, wherein in the parallel p-n layer, the second-conductivity-type partition regions are periodically formed conforming to a basic periodicity specified by a predetermined distance, and SA/S (where, SA is a sectional area per a single second-conductivity-type partition region as viewed in a plane parallel with the main surface, and S is a sectional area of a unit structural region, periodically formed as containing one of the second-conductivity-type partition regions, as viewed in a plane parallel with the main surface) in an element-forming region allowing current to flow therethrough is smaller than SA/S in at least a portion of a periphery region surrounding the element-forming region.

摘要翻译： 半导体器件具有半导体衬底和设置在半导体衬底的主表面和背表面之间的并行pn层以及交替布置在其中的第一导电型漂移区和第二导电型分隔区，其中在 平行pn层，第二导电型分隔区域周期性地形成为符合预定距离规定的基本周期，SA / S（其中，SA是每个单个第二导电型分隔区域的截面面积 在平行于主表面的平面中，S是单元结构区域的截面面积，在与元件的主表面平行的平面中周期性地形成为包含第二导电型分隔区域之一） 允许电流流过其的形成区域在围绕元件形成区域的周边区域的至少一部分中小于SA / S。

公开(公告)号：US20070052015A1

公开(公告)日：2007-03-08

申请号：US11515899

申请日：2006-09-06

申请人： Yoshinao Miura ,  Hitoshi Ninomiya

发明人： Yoshinao Miura ,  Hitoshi Ninomiya

IPC分类号： H01L29/76

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66734 ,  H01L29/7813

摘要： Aiming at realizing high breakdown voltage and low ON resistance of a semiconductor device having the super-junction structure, the semiconductor device of the present invention has a semiconductor substrate having an element forming region having a gate electrode formed therein, and a periphery region formed around the element forming region, and having an field oxide film formed therein; and a parallel p-n layer having n-type drift regions and p-type column regions alternately arranged therein, formed along the main surface of the semiconductor substrate, as being distributed over the element forming region and a part of the periphery region, wherein the periphery region has no column region formed beneath the end portion on the element forming region side of the field oxide film and has p-type column regions as at least one column region formed under the field oxide film.

摘要翻译： 为了实现具有超结结构的半导体器件的高击穿电压和低导通电阻，本发明的半导体器件具有半导体衬底，其具有形成有栅电极的元件形成区域和形成在其周围的周边区域 元件形成区域，并且其中形成有场氧化物膜; 以及沿半导体基板的主表面形成有n型漂移区和交替配置的p型列区的并行pn层，分布在元件形成区域和周边区域的一部分上，其中， 区域在场氧化膜的元件形成区域侧的端部之下没有形成列区域，并且具有作为在场氧化膜下形成的至少一个列区域的p型列区域。

公开(公告)号：US20050212053A1

公开(公告)日：2005-09-29

申请号：US11085155

申请日：2005-03-22

申请人： Yoshinao Miura ,  Hitoshi Ninomiya

发明人： Yoshinao Miura ,  Hitoshi Ninomiya

IPC分类号： H01L29/06 ,  H01L21/00 ,  H01L21/336 ,  H01L29/40 ,  H01L29/73 ,  H01L29/76 ,  H01L29/78 ,  H01L29/861 ,  H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/402 ,  H01L29/7811

摘要： The present invention provides a super-junction semiconductor element having a high voltage resistance and a low resistivity, while being successfully reduced in the size thereof, which comprises a semiconductor substrate 3; a pair of electrodes 1, 2 provided respectively on a top surface 12 and a back surface 13 of the semiconductor substrate 3; a parallel pn layer provided between the top surface 12 and the back surface 13 of said semiconductor substrate, having n-type semiconductor layers 4 allowing current flow under the ON state but being depleted under the OFF state, and p-type semiconductor layers 5 alternately arranged therein; and an insulating film 6 formed so as to surround the parallel pn layer; wherein the insulating film 6 is formed at a predetermined position.

摘要翻译： 本发明提供一种具有高耐电压性和低电阻率的超结半导体元件，同时其尺寸成功地减小，其包括半导体衬底3; 分别设置在半导体衬底3的顶表面12和背表面13上的一对电极1,2; 设置在所述半导体衬底的顶表面12和背表面13之间的平行pn层，其具有允许电流在导通状态下流动但在断开状态下耗尽的n型半导体层4和交替地p型半导体层5 布置在其中 以及形成为包围平行pn层的绝缘膜6; 其中绝缘膜6形成在预定位置。

公开(公告)号：US07432134B2

公开(公告)日：2008-10-07

申请号：US11943609

申请日：2007-11-21

申请人： Hitoshi Ninomiya ,  Yoshinao Miura

发明人： Hitoshi Ninomiya ,  Yoshinao Miura

IPC分类号： H01L21/332 ,  H01L29/04

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7813

摘要： A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming region and having an element-isolating region 118 formed therein. On the main surface of the semiconductor substrate 101, there is formed a parallel pn layer having an N-type drift region 104 and P-type column regions 106 alternately arranged therein. In the circumferential region, there is formed a field electrode 120, but the field electrode 120 is not formed on the P-type column regions 106. The P-type column regions 106 in the circumferential region are formed with a depth larger than or equal to that of the P-type column regions 106 in the element-forming region.

公开(公告)号：US20070012998A1

公开(公告)日：2007-01-18

申请号：US11483738

申请日：2006-07-11

申请人： Yoshinao Miura ,  Hitoshi Ninomiya

发明人： Yoshinao Miura ,  Hitoshi Ninomiya

IPC分类号： H01L29/76

CPC分类号： H01L29/0692 ,  H01L29/0634 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor substrate, and a parallel p-n layer provided between the main surface and the back surface of the semiconductor substrate, and first-conductivity-type drift region and second-conductivity-type partition regions alternately arranged therein, wherein in the parallel p-n layer, the second-conductivity-type partition regions are periodically formed conforming to a basic periodicity specified by a predetermined distance, and SA/S (where, SA is a sectional area per a single second-conductivity-type partition region as viewed in a plane parallel with the main surface, and S is a sectional area of a unit structural region, periodically formed as containing one of the second-conductivity-type partition regions, as viewed in a plane parallel with the main surface) in an element-forming region allowing current to flow therethrough is smaller than SA/S in at least a portion of a periphery region surrounding the element-forming region.

摘要翻译： 半导体器件具有半导体衬底和设置在半导体衬底的主表面和背表面之间的并行pn层以及交替布置在其中的第一导电型漂移区和第二导电型分隔区，其中在 平行pn层，第二导电型分隔区域周期性地形成为符合由预定距离指定的基本周期性，并且SΛA / S（其中，S < 是在与主表面平行的平面中观察到的每个单个第二导电型分隔区域的截面面积，S是单位结构区域的截面积，周期性地形成为包含第二导电型隔板 在平行于主表面的平面中观察的区域）在允许电流流过的元件形成区域中，在围绕元件的周边区域的至少一部分中小于S A / S -对于 明区。

公开(公告)号：US20060151831A1

公开(公告)日：2006-07-13

申请号：US11320950

申请日：2005-12-30

申请人： Hitoshi Ninomiya ,  Yoshinao Miura

发明人： Hitoshi Ninomiya ,  Yoshinao Miura

IPC分类号： H01L29/94

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7813

摘要： A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming region and having an element-isolating region 118 formed therein. On the main surface of the semiconductor substrate 101, there is formed a parallel pn layer having an N-type drift region 104 and P-type column regions 106 alternately arranged therein. In the circumferential region, there is formed a field electrode 120, but the field electrode 120 is not formed on the P-type column regions 106. The P-type column regions 106 in the circumferential region are formed with a depth larger than or equal to that of the P-type column regions 106 in the element-forming region.

摘要翻译： 半导体器件100包括其中形成有栅极电极108的元件形成区域和形成在元件形成区域的外周中并具有形成在其中的元件隔离区域118的周向区域。 在半导体衬底101的主表面上形成有交替布置在其中的N型漂移区104和P型列区106的平行pn层。 在圆周区域中形成有场电极120，但是在P型列区域106上不形成场电极120。 圆周区域中的P型列区域106形成为具有大于或等于元件形成区域中的P型列区域106的深度的深度。