- 专利标题: METHODS FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURES WITH REDUCED SUSCEPTIBILITY TO LATCH-UP AND SEMICONDUCTOR DEVICE STRUCTURES FORMED BY THE METHODS
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申请号: US12117371申请日: 2008-05-08
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公开(公告)号: US20080203492A1公开(公告)日: 2008-08-28
- 发明人: Ethan Harrison Cannon , Toshiharu Furukawa , Mark Charles Hakey , David Vaclav Horak , Charles William Koburger , Jimmy Konstantinos Kontos , Jack Allan Mandelman , William Robert Tonti
- 申请人: Ethan Harrison Cannon , Toshiharu Furukawa , Mark Charles Hakey , David Vaclav Horak , Charles William Koburger , Jimmy Konstantinos Kontos , Jack Allan Mandelman , William Robert Tonti
- 申请人地址: US NY Armonk
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY Armonk
- 主分类号: H01L27/092
- IPC分类号: H01L27/092
摘要:
Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression.
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