发明申请
- 专利标题: SYNCHRONOUS SEMICONDUCTOR DEVICE, AND INSPECTION SYSTEM AND METHOD FOR THE SAME
- 专利标题(中): 同步半导体器件及其检测系统及其方法
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申请号: US12112782申请日: 2008-04-30
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公开(公告)号: US20080204067A1公开(公告)日: 2008-08-28
- 发明人: Hiroyuki SUGAMOTO , Hidetoshi Tanaka , Yasushige Ogawa
- 申请人: Hiroyuki SUGAMOTO , Hidetoshi Tanaka , Yasushige Ogawa
- 专利权人: FUJITSU LIMITED
- 当前专利权人: FUJITSU LIMITED
- 优先权: JP2000-365053 20001130
- 主分类号: G01R31/28
- IPC分类号: G01R31/28 ; G11C29/00
摘要:
The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.
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