发明申请
- 专利标题: MULTIPLE ADDRESS SEQUENCE CACHE PRE-FETCHING
- 专利标题(中): 多地址序列高速缓存预处理
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申请号: US11683573申请日: 2007-03-08
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公开(公告)号: US20080222343A1公开(公告)日: 2008-09-11
- 发明人: Judson E. Veazey , Blaine D. Gaither
- 申请人: Judson E. Veazey , Blaine D. Gaither
- 主分类号: G06F12/00
- IPC分类号: G06F12/00
摘要:
A method is provided for pre-fetching data into a cache memory. A first cache-line address of each of a number of data requests from at least one processor is stored. A second cache-line address of a next data request from the processor is compared to the first cache-line addresses. If the second cache-line address is adjacent to one of the first cache-line addresses, data associated with a third cache-line address adjacent to the second cache-line address is pre-fetched into the cache memory, if not already present in the cache memory.
公开/授权文献
- US07739478B2 Multiple address sequence cache pre-fetching 公开/授权日:2010-06-15
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