A configurable microprocessor that handles low computing-intensive workloads by partitioning a single processor core into two smaller corelets. The process partitions resources of a single microprocessor core to form a plurality of corelets and assigns a set of the partitioned resources to each corelet. Each set of partitioned resources is dedicated to one corelet to allow each corelet to function independently of other corelets in the plurality of corelets. The process also combines a plurality of corelets into a single microprocessor core by combining corelet resources to form a single microprocessor core. The combined resources feed the single microprocessor core.