公开(公告)号：US08418180B2

公开(公告)日：2013-04-09

申请号：US12129876

申请日：2008-05-30

申请人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

发明人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

IPC分类号： G06F9/46

CPC分类号： G06F9/30101 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4818 ,  G06F9/485

摘要： A method, apparatus, and computer program product are disclosed for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles by selecting the first thread to be a primary thread and the second thread to be a secondary thread. If a condition exists that requires overriding, an override state is executed by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.

摘要翻译： 公开了一种用于确保同时多线程（SMT）微处理器中的处理公平性的方法，装置和计算机程序产品。 在通过选择作为主线程的第一线程和第二线程成为辅线程的持续期望的时钟周期数的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。 如果存在需要覆盖的条件，则通过选择作为主线程的第二个线程和第一个线程作为辅助线程来执行覆盖状态。 超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。 响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。

公开(公告)号：US20080250226A1

公开(公告)日：2008-10-09

申请号：US11696363

申请日：2007-04-04

申请人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy

发明人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy

IPC分类号： G06F15/00

CPC分类号： G06F9/3851 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3885

摘要： A multi-mode register rename mechanism which allows a simultaneous multi-threaded processor to support full out-of-order thread execution when the number of threads is low and in-order thread execution when the number of threads increases. Responsive to changing an execution mode of a processor to operate in in-order thread execution mode, the illustrative embodiments switch a physical register in the data processing system to an architected facility, thereby forming a switched physical register. When an instruction is issued to an execution unit, wherein the issued instruction comprises a thread bit, the thread bit is examined to determine if the instruction accesses an architected facility. If the issued instruction accesses an architected facility, the instruction is executed, and the results of the executed instruction are written to the switched physical register.

摘要翻译： 多模式寄存器重命名机制，允许同时多线程处理器在线程数量低时支持完全无序的线程执行，并且当线程数增加时按顺序执行线程。 响应于改变处理器的执行模式以按顺序执行线程执行模式，所述说明性实施例将数据处理系统中的物理寄存器切换到架构设施，从而形成切换的物理寄存器。 当向执行单元发出指令时，其中发出的指令包括一个线程位，检查该线程位以确定该指令是否访问一个架构设施。 如果发出的指令访问架构设施，则执行该指令，并且将所执行的指令的结果写入切换的物理寄存器。

公开(公告)号：US20080229065A1

公开(公告)日：2008-09-18

申请号：US11685428

申请日：2007-03-13

申请人： Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy

发明人： Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy

IPC分类号： G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/5061 ,  G06F2209/5012

摘要： A configurable microprocessor which combines a plurality of corelets into a single microprocessor core to handle high computing-intensive workloads. The process first selects two or more corelets in the plurality of corelets. The process combines resources of the two or more corelets to form combined resources, wherein each combined resource comprises a larger amount of a resource available to each individual corelet. The process then forms a single microprocessor core from the two or more corelets by assigning the combined resources to the single microprocessor core, wherein the combined resources are dedicated to the single microprocessor core, and wherein the single microprocessor core processes instructions with the dedicated combined resources.

摘要翻译： 一种可配置的微处理器，将多个核心组合成单个微处理器核心，以处理高计算密集型工作负载。 该过程首先在多个核心中选择两个或更多个核心。 该过程组合两个或更多个核心小区的资源以形成组合的资源，其中每个组合的资源包括更大量的可用于每个单个小堆的资源。 然后，该过程通过将组合的资源分配给单个微处理器核心而从两个或更多个核心小区形成单个微处理器核心，其中组合资源专用于单个微处理器核心，并且其中单个微处理器核心使用专用组合资源来处理指令 。

公开(公告)号：US20080229058A1

公开(公告)日：2008-09-18

申请号：US11685422

申请日：2007-03-13

申请人： Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy

发明人： Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy

IPC分类号： G06F15/76

CPC分类号： G06F9/5061 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/3897

摘要： A configurable microprocessor that handles low computing-intensive workloads by partitioning a single processor core into two smaller corelets. The process partitions resources of a single microprocessor core to form a plurality of corelets and assigns a set of the partitioned resources to each corelet. Each set of partitioned resources is dedicated to one corelet to allow each corelet to function independently of other corelets in the plurality of corelets. The process also combines a plurality of corelets into a single microprocessor core by combining corelet resources to form a single microprocessor core. The combined resources feed the single microprocessor core.

摘要翻译： 一个可配置的微处理器，通过将单个处理器内核分成两个较小的核心处理器来处理低计算密集型工作负载。 该过程分割单个微处理器核心的资源以形成多个核心小区，并将一组分割的资源分配给每个小核。 每组分区资源专用于一个corelet，以允许每个corelet独立于多个corelet中的其他corelet进行运行。 该过程还通过组合核心资源来形成单个微处理器核心，将多个核心组合成单个微处理器核心。 组合的资源馈送单个微处理器内核。

公开(公告)号：US07631308B2

公开(公告)日：2009-12-08

申请号：US11055850

申请日：2005-02-11

申请人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

发明人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

IPC分类号： G06F9/46

CPC分类号： G06F9/30101 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4818 ,  G06F9/485

摘要： A method is disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread.

摘要翻译： 在数据处理系统中公开了一种用于确保在每个时钟周期期间同时执行多个线程的同时多线程（SMT）微处理器中的处理公平性的方法。 在持续预期数量的时钟周期的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。 在标准选择状态期间，根据标准选择定义分配时钟周期优先级，通过在标准选择状态期间选择作为主线程的第一线程和第二线程作为次线程。 如果存在需要覆盖标准选择定义的条件，则执行超越状态，在该状态期间，通过选择第二个线程作为主线程，并将第一个线程作为次要线程来覆盖标准选择定义。

公开(公告)号：US20080294884A1

公开(公告)日：2008-11-27

申请号：US12129876

申请日：2008-05-30

申请人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

发明人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

IPC分类号： G06F9/30

CPC分类号： G06F9/30101 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4818 ,  G06F9/485

摘要： A method, apparatus, and computer program product are disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.

摘要翻译： 在数据处理系统中公开了一种方法，装置和计算机程序产品，用于确保在每个时钟周期期间同时执行多个线程的同时多线程（SMT）微处理器中的处理公平性。 在持续预期数量的时钟周期的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。 在标准选择状态期间，根据标准选择定义分配时钟周期优先级，通过在标准选择状态期间选择作为主线程的第一线程和第二线程作为次线程。 如果存在需要覆盖标准选择定义的条件，则执行超越状态，在该状态期间，通过选择第二个线程作为主线程，并将第一个线程作为次要线程来覆盖标准选择定义。 超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。 响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。

公开(公告)号：US08347068B2

公开(公告)日：2013-01-01

申请号：US11696363

申请日：2007-04-04

申请人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy

发明人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3885

摘要： A multi-mode register rename mechanism which allows a simultaneous multi-threaded processor to support full out-of-order thread execution when the number of threads is low and in-order thread execution when the number of threads increases. Responsive to changing an execution mode of a processor to operate in in-order thread execution mode, the illustrative embodiments switch a physical register in the data processing system to an architected facility, thereby forming a switched physical register. When an instruction is issued to an execution unit, wherein the issued instruction comprises a thread bit, the thread bit is examined to determine if the instruction accesses an architected facility. If the issued instruction accesses an architected facility, the instruction is executed, and the results of the executed instruction are written to the switched physical register.

摘要翻译： 多模式寄存器重命名机制，允许同时多线程处理器在线程数量低时支持完全无序的线程执行，并且当线程数增加时按顺序执行线程。 响应于改变处理器的执行模式以按顺序执行线程执行模式，所述说明性实施例将数据处理系统中的物理寄存器切换到架构设施，从而形成切换的物理寄存器。 当向执行单元发出指令时，其中发出的指令包括一个线程位，检查该线程位以确定该指令是否访问一个架构设施。 如果发出的指令访问架构设施，则执行该指令，并且将所执行的指令的结果写入切换的物理寄存器。

公开(公告)号：US20090063898A1

公开(公告)日：2009-03-05

申请号：US12270300

申请日：2008-11-13

申请人： Susan Elizabeth Eisen ,  Hung Qui Le ,  Michael James Mack ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney

发明人： Susan Elizabeth Eisen ,  Hung Qui Le ,  Michael James Mack ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney

IPC分类号： G06F11/20

CPC分类号： G06F12/0888 ,  G06F9/30043 ,  G06F9/3851 ,  G06F9/3863 ,  G06F11/1407

摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.

摘要翻译： 恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。 恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。 处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。 允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。 如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

公开(公告)号：US07490226B2

公开(公告)日：2009-02-10

申请号：US11054289

申请日：2005-02-09

申请人： Hung Qui Le ,  Dung Quoc Nguyen ,  Raymond Cheung Yeung

发明人： Hung Qui Le ,  Dung Quoc Nguyen ,  Raymond Cheung Yeung

IPC分类号： G06F9/312

CPC分类号： G06F9/383 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3867

摘要： A method and related apparatus is provided for a processor having a number of registers, wherein instructions are sequentially issued to move through a sequence of execution stages, from an initial stage to a final write back stage. As a method, an embodiment includes the step of issuing a first instruction, such as an FMA instruction, to move through the sequence of execution stages, the first instruction being directed to a specified one of the registers. The method further includes issuing a second instruction to move through the execution stages, the second instruction being issued after the first instruction has issued, but before the first instruction reaches the final write back stage. The second instruction is likewise directed to the specified register, and comprises either a store instruction or a load instruction, selectively. R and W bits corresponding to the specified register are used to ensure that a store instruction does not read data from, and that a load instruction does not write data to the specified register, respectively, before the first instruction is moved to the final write back stage.

摘要翻译： 提供了一种用于具有多个寄存器的处理器的方法和相关装置，其中顺序地发出指令以从初始阶段到最终回写阶段移动经过一系列执行阶段。 作为一种方法，实施例包括发出诸如FMA指令的第一指令以移动经过执行级序列的步骤，第一指令被引导到指定的一个寄存器。 该方法还包括发出第二指令以移动通过执行阶段，第二指令在第一指令发出之后但在第一指令到达最终回写阶段之前发出。 第二条指令同样针对指定的寄存器，并且选择性地包括存储指令或加载指令。 使用与指定寄存器相对应的R和W位来确保存储指令不会从第一指令移动到最终回写之前分别读取数据，并且加载指令不会将数据写入指定的寄存器 阶段。

公开(公告)号：US07467325B2

公开(公告)日：2008-12-16

申请号：US11055258

申请日：2005-02-10

申请人： Susan Elizabeth Eisen ,  Hung Qui Le ,  Michael James Mack ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney

发明人： Susan Elizabeth Eisen ,  Hung Qui Le ,  Michael James Mack ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney

IPC分类号： G06F11/00

CPC分类号： G06F12/0888 ,  G06F9/30043 ,  G06F9/3851 ,  G06F9/3863 ,  G06F11/1407

摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.

摘要翻译： 恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。 恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。 处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。 允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。 如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。