发明申请
- 专利标题: METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
- 专利标题(中): 制造半导体集成电路器件的方法
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申请号: US12128796申请日: 2008-05-29
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公开(公告)号: US20080237752A1公开(公告)日: 2008-10-02
- 发明人: Hiroshi Kujirai , Kousuke Okuyama , Kazuhiro Hata , Kiyonori Oyu , Ryo Nagai , Hiroyuki Uchiyama , Takahiro Kumauchi , Teruhisa Ichise
- 申请人: Hiroshi Kujirai , Kousuke Okuyama , Kazuhiro Hata , Kiyonori Oyu , Ryo Nagai , Hiroyuki Uchiyama , Takahiro Kumauchi , Teruhisa Ichise
- 优先权: JP2001-253028 20010823
- 主分类号: H01L49/00
- IPC分类号: H01L49/00
摘要:
Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.
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