公开(公告)号：US07687849B2

公开(公告)日：2010-03-30

申请号：US12128796

申请日：2008-05-29

申请人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

发明人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

IPC分类号： H01L29/788

CPC分类号： H01L29/4983 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10873 ,  H01L29/4941

摘要： Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

摘要翻译： 公开了一种通过减少组成MISFET的多金属栅极的金属的污染来减少泄漏电流的技术。 在p型阱（半导体衬底），帽绝缘膜，W膜和WN膜上的栅绝缘膜上形成的多晶硅膜，WN膜，W膜和帽绝缘膜是 进行蚀刻，并对其下面的多晶硅膜进行过蚀刻。 然后，在这些膜的侧壁上形成侧壁膜。 此后，在以侧壁膜为掩模蚀刻多晶硅膜之后，在氧化气氛中进行热处理，在多晶硅膜的侧壁上形成有氧化膜。 结果，可以减少由W和W氧化物引起的栅绝缘膜上的污染，并且这些材料向半导体衬底（p型阱）的扩散以及由此导致的漏电流的增加 被阻止

公开(公告)号：US06828242B2

公开(公告)日：2004-12-07

申请号：US10223317

申请日：2002-08-20

申请人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

发明人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

IPC分类号： H01L21302

CPC分类号： H01L29/4983 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10873 ,  H01L29/4941

摘要： Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

摘要翻译： 公开了通过减少组成MISFET的多金属栅极的金属的污染来减少泄漏电流的技术。 在p型阱（半导体衬底），帽绝缘膜，W膜和WN膜上的栅绝缘膜上形成的多晶硅膜，WN膜，W膜和帽绝缘膜是 进行蚀刻，并对其下面的多晶硅膜进行过蚀刻。 然后，在这些膜的侧壁上形成侧壁膜。 此后，在以侧壁膜为掩模蚀刻多晶硅膜之后，在氧化气氛中进行热处理，在多晶硅膜的侧壁上形成有氧化膜。 结果，可以减少由W和W氧化物引起的栅绝缘膜上的污染，并且这些材料向半导体衬底（p型阱）的扩散以及由此导致的漏电流的增加 被阻止

公开(公告)号：US07224034B2

公开(公告)日：2007-05-29

申请号：US10978469

申请日：2004-11-02

申请人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

发明人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

IPC分类号： H01L29/76

CPC分类号： H01L29/4983 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10873 ,  H01L29/4941

摘要： Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET: Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

摘要翻译： 公开了一种通过减少组成MISFET的多金属栅极的金属的污染来减少泄漏电流的技术：在p上的栅极绝缘膜上形成的多晶硅膜，WN膜，W膜和帽绝缘膜 （半导体衬底），帽绝缘膜，W膜和WN膜被蚀刻，并且进行其下面的多晶硅膜的过蚀刻。 然后，在这些膜的侧壁上形成侧壁膜。 此后，在以侧壁膜为掩模蚀刻多晶硅膜之后，在氧化气氛中进行热处理，在多晶硅膜的侧壁上形成有氧化膜。 结果，可以减少由W和W氧化物引起的栅绝缘膜上的污染，并且这些材料向半导体衬底（p型阱）的扩散以及由此导致的漏电流的增加 被阻止

公开(公告)号：US20080237752A1

公开(公告)日：2008-10-02

申请号：US12128796

申请日：2008-05-29

申请人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

发明人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

IPC分类号： H01L49/00

CPC分类号： H01L29/4983 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10873 ,  H01L29/4941

摘要： Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

摘要翻译： 公开了通过减少组成MISFET的多金属栅极的金属的污染来减少泄漏电流的技术。 在p型阱（半导体衬底），帽绝缘膜，W膜和WN膜上的栅绝缘膜上形成的多晶硅膜，WN膜，W膜和帽绝缘膜是 进行蚀刻，并对其下面的多晶硅膜进行过蚀刻。 然后，在这些膜的侧壁上形成侧壁膜。 此后，在以侧壁膜为掩模蚀刻多晶硅膜之后，在氧化气氛中进行热处理，在多晶硅膜的侧壁上形成有氧化膜。 结果，可以减少由W和W氧化物引起的栅绝缘膜上的污染，并且这些材料向半导体衬底（p型阱）的扩散以及由此导致的漏电流的增加 被阻止

公开(公告)号：US20050087880A1

公开(公告)日：2005-04-28

申请号：US10978469

申请日：2004-11-02

申请人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

发明人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

IPC分类号： H01L21/768 ,  H01L21/28 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L29/49 ,  H01L29/78 ,  H01L23/48

CPC分类号： H01L29/4983 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10873 ,  H01L29/4941

摘要： Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET: Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

摘要翻译： 公开了一种通过减少组成MISFET的多金属栅极的金属的污染来减少泄漏电流的技术：在p上的栅极绝缘膜上形成的多晶硅膜，WN膜，W膜和帽绝缘膜 （半导体衬底），帽绝缘膜，W膜和WN膜被蚀刻，并且进行其下面的多晶硅膜的过蚀刻。 然后，在这些膜的侧壁上形成侧壁膜。 此后，在以侧壁膜为掩模蚀刻多晶硅膜之后，在氧化气氛中进行热处理，在多晶硅膜的侧壁上形成有氧化膜。 结果，可以减少由W和W氧化物引起的栅绝缘膜上的污染，并且这些材料向半导体衬底（p型阱）的扩散以及由此导致的漏电流的增加 被阻止

公开(公告)号：US07417291B2

公开(公告)日：2008-08-26

申请号：US11785463

申请日：2007-04-18

申请人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

发明人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

IPC分类号： H01L29/76

CPC分类号： H01L29/4983 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10873 ,  H01L29/4941

摘要： Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

摘要翻译： 公开了通过减少组成MISFET的多金属栅极的金属的污染来减少泄漏电流的技术。 在p型阱（半导体衬底），帽绝缘膜，W膜和WN膜上的栅绝缘膜上形成的多晶硅膜，WN膜，W膜和帽绝缘膜是 进行蚀刻，并对其下面的多晶硅膜进行过蚀刻。 然后，在这些膜的侧壁上形成侧壁膜。 此后，在以侧壁膜为掩模蚀刻多晶硅膜之后，在氧化气氛中进行热处理，在多晶硅膜的侧壁上形成有氧化膜。 结果，可以减少由W和W氧化物引起的栅绝缘膜上的污染，并且这些材料向半导体衬底（p型阱）的扩散以及由此导致的漏电流的增加 被阻止

公开(公告)号：US20070187783A1

公开(公告)日：2007-08-16

申请号：US11785463

申请日：2007-04-18

申请人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

发明人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

IPC分类号： H01L29/94

CPC分类号： H01L29/4983 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10873 ,  H01L29/4941

摘要： Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

摘要翻译： 公开了通过减少组成MISFET的多金属栅极的金属的污染来减少泄漏电流的技术。 在p型阱（半导体衬底），帽绝缘膜，W膜和WN膜上的栅绝缘膜上形成的多晶硅膜，WN膜，W膜和帽绝缘膜是 进行蚀刻，并对其下面的多晶硅膜进行过蚀刻。 然后，在这些膜的侧壁上形成侧壁膜。 此后，在以侧壁膜为掩模蚀刻多晶硅膜之后，在氧化气氛中进行热处理，在多晶硅膜的侧壁上形成有氧化膜。 结果，可以减少由W和W氧化物引起的栅绝缘膜上的污染，并且这些材料向半导体衬底（p型阱）的扩散以及由此导致的漏电流的增加 被阻止

公开(公告)号：US07256085B2

公开(公告)日：2007-08-14

申请号：US11077233

申请日：2005-03-11

申请人： Kazuhiro Hata ,  Shinichi Sato ,  Yukiharu Akiyama

发明人： Kazuhiro Hata ,  Shinichi Sato ,  Yukiharu Akiyama

IPC分类号： H01L21/8238

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L27/11568 ,  H01L29/66825

摘要： A manufacturing method of a semiconductor memory device comprising the steps of: forming plural trenches in stripes in a semiconductor substrate and filling each of the trenches with an element isolation insulating film to form element isolation regions; sequentially forming a tunnel insulating film and a charge-storable film so as to cover active regions between the element isolation regions; forming an interlayer insulating film on the charge-storable film; forming plural control gates on the interlayer insulating film in a direction orthogonal to a longitudinal direction of the trenches; among source formation regions and drain formation regions alternately provided between the plural control gates, etching the element isolation insulating film in the source formation regions, using as a mask a resist film having openings in the source formation regions, to expose surfaces of the trenches; and carrying out isotropic plasma ion implantation on the source formation regions to form source diffusion layers in the surfaces of the trenches and in the active regions.

摘要翻译： 一种半导体存储器件的制造方法，包括以下步骤：在半导体衬底中形成条纹中的多个沟槽，并用元件隔离绝缘膜填充每个沟槽以形成元件隔离区域; 依次形成隧道绝缘膜和电荷存储膜，以覆盖元件隔离区之间的有源区; 在电荷存储膜上形成层间绝缘膜; 在与所述沟槽的纵向正交的方向上在所述层间绝缘膜上形成多个控制栅极; 在多个控制栅极之间交替设置的源极形成区域和漏极形成区域之间，在源极形成区域中蚀刻元件隔离绝缘膜，使用在源极形成区域中具有开口的抗蚀剂膜作为掩模来暴露沟槽的表面; 并在源极形成区域上进行各向同性等离子体离子注入，以在沟槽表面和活性区域中形成源极扩散层。

公开(公告)号：US06513120B2

公开(公告)日：2003-01-28

申请号：US09193630

申请日：1998-11-17

申请人： Hiroshi Kanzawa ,  Kazuhiro Hata

发明人： Hiroshi Kanzawa ,  Kazuhiro Hata

IPC分类号： G06F1130

CPC分类号： H04L63/105 ,  G06F21/313 ,  H04L63/20

摘要： A transmission device including an advanced security system is provided to specify an illegally operated device, inhibit the illegal operations, prevent from forgetting to unlock a log-in status by a maintenance operator, and set permitted user level for each command. The security system for a transmission device in a network is formed with plural transmission devices each including, at least, a port for a control terminal, which controls the transmission devices, when a cable disconnection is detected in a port of one transmission device, a log-in status is unlocked for the one transmission device or the other transmission devices through the port.

摘要翻译： 提供包括高级安全系统的发送装置，以指定非法操作的装置，禁止非法操作，防止维护操作者忘记解锁登录状态，并为每个命令设置允许的用户级别。 网络中的传输设备的安全系统形成有多个传输设备，每个传输设备至少包括控制终端的端口，用于控制传输设备，当在一个传输设备的端口中检测到电缆断开时， 通过端口为一个传输设备或其他传输设备解锁登录状态。

公开(公告)号：USD307577S

公开(公告)日：1990-05-01

申请号：US139058

申请日：1987-12-29

申请人： Yoshinori Abe ,  Muneaki Inoue ,  Kazuhiro Hata

设计人： Yoshinori Abe ,  Muneaki Inoue ,  Kazuhiro Hata