发明申请
- 专利标题: METHOD FOR PLANARIZING AN INSULATION LAYER IN A SEMICONDUCTOR DEVICE CAPABLE OF OMITTING A MASK PROCESS AND AN ETCHING PROCESS
- 专利标题(中): 用于在掩蔽过程和蚀刻过程的半导体器件中平面化绝缘层的方法
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申请号: US11939631申请日: 2007-11-14
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公开(公告)号: US20080242084A1公开(公告)日: 2008-10-02
- 发明人: Hyung Hwan KIM , Jong Goo JUNG
- 申请人: Hyung Hwan KIM , Jong Goo JUNG
- 优先权: KR10-2007-0031926 20070330
- 主分类号: H01L21/4763
- IPC分类号: H01L21/4763
摘要:
In a method for planarizing an insulation layer in a semiconductor device, an insulation layer is formed over a semiconductor substrate having a cell region and a peripheral region. The cell region is higher than the peripheral region due to a capacitor formed in the cell region. A metal layer is formed over the insulation layer. The metal layer is chemical mechanical polished to expose the insulation layer portion in the cell region. The exposed insulation layer portion in the cell region is chemical mechanical polishing to planarize the insulation layer, and the planarized insulation layer and the remaining metal layer are chemical mechanical polishing to remove the metal layer remained in the peripheral region. The method for planarizing an insulation layer does not require a separate photosensitive layer forming process or a dry etching process.
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