公开(公告)号：US07855109B2

公开(公告)日：2010-12-21

申请号：US12345755

申请日：2008-12-30

申请人： Hyung Hwan Kim ,  Kwang Kee Chae ,  Jong Goo Jung ,  Ok Min Moon ,  Young Bang Lee ,  Sung Eun Park

发明人： Hyung Hwan Kim ,  Kwang Kee Chae ,  Jong Goo Jung ,  Ok Min Moon ,  Young Bang Lee ,  Sung Eun Park

IPC分类号： H01L21/337

CPC分类号： H01L21/76232

摘要： A method for manufacturing a semiconductor device according to the present invention, comprising the steps of: forming a screen oxide layer over the surface of an active region of a semiconductor substrate in which an isolation structure defining the active region is formed; forming a first recess pattern in the active region and a second recess pattern in the isolation structure by etching a gate forming area in the active region and the isolation structure part extended thereto; removing the screen oxide film and simultaneously expanding the width of the second recess pattern; forming a first insulation dielectric layer over the resultant of the substrate having the second recess pattern with the expanded width so that the first insulation dielectric layer is blocked at the upper end thereof in the first recess pattern and it is deposited along the profile in the second recess pattern; forming a second insulation dielectric layer over the first insulation dielectric layer so that the second recess patter is not filled; forming a third insulation dielectric layer over the second insulation dielectric layer so that the second recess pattern is filled; and removing the third, second, and first insulation dielectric layers formed over the active region including the first recess pattern and the isolation structure between the second recess patterns.

摘要翻译： 一种根据本发明的半导体器件的制造方法，包括以下步骤：在其中形成限定有源区的隔离结构的半导体衬底的有源区的表面上形成屏蔽氧化物层; 通过蚀刻有源区域中的栅极形成区域和延伸到其中的隔离结构部分，在有源区域中形成第一凹槽图案和隔离结构中的第二凹陷图案; 去除屏幕氧化膜并同时扩大第二凹槽图案的宽度; 在具有第二凹槽图案的基底的结果上形成第一绝缘电介质层，其具有扩展的宽度，使得第一绝缘电介质层在其第一凹槽图案的上端处被阻挡，并且沿着第二凹部图案 休闲模式; 在所述第一绝缘电介质层上形成第二绝缘电介质层，使得所述第二凹槽图案不被填充; 在所述第二绝缘电介质层上形成第三绝缘电介质层，使得所述第二凹槽图案被填充; 以及去除在包括第一凹槽图案的有源区域和在第二凹槽图案之间的隔离结构之间形成的第三绝缘介电层和第二绝缘介电层。

公开(公告)号：US07018924B2

公开(公告)日：2006-03-28

申请号：US10603976

申请日：2003-06-25

申请人： Jong Goo Jung ,  Sang Ick Lee

发明人： Jong Goo Jung ,  Sang Ick Lee

IPC分类号： H01L21/4763 ,  C09K13/04

CPC分类号： C09G1/02 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/7684

摘要： CMP slurries for oxide film and a method for forming a metal line contact plug of a semiconductor device are described herein. When a polishing process of a multi-layer film is performed by using the disclosed CMP slurry for oxide film including an HXOn compound (wherein n is an integer from 1 to 4), a stable landing plug poly can be formed by preventing step differences by reducing interlayer polishing speed differences.

摘要翻译： 本文描述了用于氧化物膜的CMP浆料和用于形成半导体器件的金属线接触插塞的方法。 当通过使用所公开的包括HXO N n化合物（其中n是1至4的整数）的氧化物膜的CMP浆料进行多层膜的抛光工艺时，稳定的着色插塞聚 可以通过减少层间抛光速度差来防止台阶差来形成。

公开(公告)号：US20100151656A1

公开(公告)日：2010-06-17

申请号：US12345755

申请日：2008-12-30

申请人： Hyung Hwan KIM ,  Kwang Kee CHAE ,  Jong Goo JUNG ,  Ok Min MOON ,  Young Bang LEE ,  Sung Eun PARK

发明人： Hyung Hwan KIM ,  Kwang Kee CHAE ,  Jong Goo JUNG ,  Ok Min MOON ,  Young Bang LEE ,  Sung Eun PARK

IPC分类号： H01L21/762

CPC分类号： H01L21/76232

摘要： A method for manufacturing a semiconductor device according to the present invention, comprising the steps of: forming a screen oxide layer over the surface of an active region of a semiconductor substrate in which an isolation structure defining the active region is formed; forming a first recess pattern in the active region and a second recess pattern in the isolation structure by etching a gate forming area in the active region and the isolation structure part extended thereto; removing the screen oxide film and simultaneously expanding the width of the second recess pattern; forming a first insulation dielectric layer over the resultant of the substrate having the second recess pattern with the expanded width so that the first insulation dielectric layer is blocked at the upper end thereof in the first recess pattern and it is deposited along the profile in the second recess pattern; forming a second insulation dielectric layer over the first insulation dielectric layer so that the second recess patter is not filled; forming a third insulation dielectric layer over the second insulation dielectric layer so that the second recess pattern is filled; and removing the third, second, and first insulation dielectric layers formed over the active region including the first recess pattern and the isolation structure between the second recess patterns.

摘要翻译： 一种根据本发明的半导体器件的制造方法，包括以下步骤：在其中形成限定有源区的隔离结构的半导体衬底的有源区的表面上形成屏蔽氧化物层; 通过蚀刻有源区域中的栅极形成区域和延伸到其中的隔离结构部分，在有源区域中形成第一凹槽图案和隔离结构中的第二凹陷图案; 去除屏幕氧化膜并同时扩大第二凹槽图案的宽度; 在具有第二凹槽图案的基底的结果上形成第一绝缘电介质层，其具有扩展的宽度，使得第一绝缘电介质层在其第一凹槽图案的上端处被阻挡，并且沿着第二凹部图案 休闲模式; 在所述第一绝缘电介质层上形成第二绝缘电介质层，使得所述第二凹槽图案不被填充; 在所述第二绝缘电介质层上形成第三绝缘电介质层，使得所述第二凹槽图案被填充; 以及去除在包括第一凹槽图案的有源区域和在第二凹槽图案之间的隔离结构之间形成的第三绝缘介电层和第二绝缘介电层。

公开(公告)号：US20090267199A1

公开(公告)日：2009-10-29

申请号：US12167322

申请日：2008-07-03

申请人： Hyung Hwan KIM ,  Kwang Kee CHAE ,  Jong Goo JUNG ,  Ok Min MOON ,  Young Bang LEE ,  Sung Eun PARK

发明人： Hyung Hwan KIM ,  Kwang Kee CHAE ,  Jong Goo JUNG ,  Ok Min MOON ,  Young Bang LEE ,  Sung Eun PARK

IPC分类号： H01L21/762 ,  H01L23/58

CPC分类号： H01L21/76232

摘要： An isolation layer of a semiconductor device and a process for forming the same is described herein. The isolation layer includes a trench that is defined and formed in a semiconductor substrate. A first liner nitride layer is formed on the surface of the trench and a flowable insulation layer is formed in the trench including the first liner nitride layer. The flowable insulation layer is formed such to define a recess in the trench. A second liner nitride layer is formed on the recess including the flowable insulation layer and the first liner nitride layer. Finally, an insulation layer is formed in the recess on the second liner nitride layer to completely fill the trench.

摘要翻译： 本文描述了半导体器件的隔离层及其形成工艺。 隔离层包括限定并形成在半导体衬底中的沟槽。 第一衬里氮化物层形成在沟槽的表面上，并且在包括第一衬里氮化物层的沟槽中形成可流动的绝缘层。 可流动绝缘层形成为在沟槽中限定凹部。 在包括可流动绝缘层和第一衬里氮化物层的凹部上形成第二衬里氮化物层。 最后，在第二衬里氮化物层上的凹槽中形成绝缘层以完全填充沟槽。

公开(公告)号：US07199053B2

公开(公告)日：2007-04-03

申请号：US10876686

申请日：2004-06-28

申请人： Jong Goo Jung

发明人： Jong Goo Jung

IPC分类号： H01L21/461

CPC分类号： H01L21/31053

摘要： Disclosed is a method for detecting an end-point of a CMP process of a semiconductor device. More specifically, when all polishing processes are performed using a nitride film as a polishing barrier film, a buffer layer including nitrogen is formed on the nitride film and a polishing process is performed. Then, the concentration of NO from ammonia gas generated from the buffer layer is detected so that the nitride film may be polished to a desired target without damage of the nitride film. As a result, an end-point can be set.

摘要翻译： 公开了一种用于检测半导体器件的CMP工艺的端点的方法。 更具体地，当使用氮化物膜作为抛光阻挡膜进行所有抛光工艺时，在氮化物膜上形成包括氮的缓冲层，并进行抛光处理。 然后，检测从缓冲层产生的氨气中的NO浓度，使得氮化物膜可以抛光到所需目标而不损害氮化物膜。 因此，可以设置端点。

公开(公告)号：US06864177B2

公开(公告)日：2005-03-08

申请号：US10329938

申请日：2002-12-26

申请人： Jong Goo Jung ,  Ki Cheol Ahn ,  Pan Ki Kwon

发明人： Jong Goo Jung ,  Ki Cheol Ahn ,  Pan Ki Kwon

IPC分类号： H01L21/28 ,  C09G1/02 ,  H01L21/321 ,  H01L21/60 ,  H01L21/461 ,  H01L21/302

CPC分类号： H01L21/76897 ,  C09G1/02 ,  H01L21/3212

摘要： A method for manufacturing of a metal line contact plug of a semiconductor device by performing a two step CMP process using (1) a first slurry solution having high etching selectivity of metal/insulating film and (2) a second slurry solution having small etching selectivity of metal/insulating film, thereby minimizing dependency on CMP devices and separating easily a metal line contact plug.

摘要翻译： 一种半导体器件的金属线接触插塞的制造方法，其特征在于，使用（1）金属/绝缘膜的蚀刻选择性高的第一浆料溶液和（2）具有小蚀刻选择性的第二浆液 的金属/绝缘膜，从而最小化对CMP器件的依赖性，并且容易地分离金属线接触插塞。

公开(公告)号：US08252686B2

公开(公告)日：2012-08-28

申请号：US12427870

申请日：2009-04-22

申请人： Hyung Soon Park ,  Noh Jung Kwak ,  Seung Jin Yeom ,  Choon Kun Ryu ,  Jong Goo Jung ,  Sung Jun Kim

发明人： Hyung Soon Park ,  Noh Jung Kwak ,  Seung Jin Yeom ,  Choon Kun Ryu ,  Jong Goo Jung ,  Sung Jun Kim

IPC分类号： H01L21/302

CPC分类号： H01L21/02074 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76883

摘要： A process for forming a copper wiring and the prevention of copper ion migration in a semiconductor device is disclosed herein. The process includes conducting a post-cleaning process for a copper layer that is to form the cooper wiring after already having undergone a CMP process. The post-cleaning process includes conducting a primary chemical cleaning using a citric acid-based chemical. A secondary chemical cleaning is then conducted on the copper layer having undergone the primary chemical cleaning using an ascorbic acid-based chemical. After the post-cleaning process is completed, the migration of copper ions over time is prevented thereby improving the reliability of the semiconductor device.

摘要翻译： 本文公开了一种用于形成铜布线的方法和防止半导体器件中的铜离子迁移。 该方法包括在已经经过CMP工艺的铜层之后对铜层进行后清洗处理。 后清洗过程包括使用基于柠檬酸的化学品进行初级化学清洗。 然后在使用抗坏血酸的化学品进行了主要化学清洗的铜层上进行二次化学清洗。 在完成后清洗处理之后，防止了铜离子随时间的迁移，从而提高了半导体器件的可靠性。

公开(公告)号：US07056803B2

公开(公告)日：2006-06-06

申请号：US10879508

申请日：2004-06-30

申请人： Jong Goo Jung ,  Hyung Soon Park

发明人： Jong Goo Jung ,  Hyung Soon Park

IPC分类号： H01L21/20

CPC分类号： H01L28/91 ,  H01L27/10814 ,  H01L27/10852

摘要： Disclosed is a method for forming a capacitor of a semiconductor device. The method comprises the steps of: forming a nitride film for storage electrode on a semiconductor substrate; forming an oxide film for storage electrode on the nitride film; selectively etching the oxide film and the nitride film to define a storage electrode region; forming a conductive layer for storage electrode on the semiconductor substrate including the storage electrode region; forming a gap-filling nitride film on the semiconductor substrate to fill up the storage electrode region; performing a CMP process using the oxide film as a polishing stop layer to form a storage electrode; and removing the gap-filling nitride film.

摘要翻译： 公开了一种形成半导体器件的电容器的方法。 该方法包括以下步骤：在半导体衬底上形成用于存储电极的氮化物膜; 在氮化膜上形成用于存储电极的氧化膜; 选择性地蚀刻氧化膜和氮化物膜以限定存储电极区域; 在包括所述存储电极区域的所述半导体衬底上形成用于存储电极的导电层; 在所述半导体衬底上形成间隙填充氮化物膜以填满所述存储电极区域; 使用氧化膜作为抛光停止层进行CMP处理以形成存储电极; 并去除间隙填充氮化物膜。

公开(公告)号：US20100210104A1

公开(公告)日：2010-08-19

申请号：US12427870

申请日：2009-04-22

申请人： Hyung Soon Park ,  Noh Jung Kwak ,  Seung Jin Yeom ,  Choon Kun Ryu ,  Jong Goo Jung ,  Sung Jun Kim

发明人： Hyung Soon Park ,  Noh Jung Kwak ,  Seung Jin Yeom ,  Choon Kun Ryu ,  Jong Goo Jung ,  Sung Jun Kim

IPC分类号： H01L21/768 ,  H01L21/306

CPC分类号： H01L21/02074 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76883

摘要： A process for forming a copper wiring and the prevention of copper ion migration in a semiconductor device is disclosed herein. The process includes conducting a post-cleaning process for a copper layer that is to form the cooper wiring after already having undergone a CMP process. The post-cleaning process includes conducting a primary chemical cleaning using a citric acid-based chemical. A secondary chemical cleaning is then conducted on the copper layer having undergone the primary chemical cleaning using an ascorbic acid-based chemical. After the post-cleaning process is completed, the migration of copper ions over time is prevented thereby improving the reliability of the semiconductor device.

摘要翻译： 本文公开了一种用于形成铜布线的方法和防止半导体器件中的铜离子迁移。 该方法包括对经过CMP工艺形成铜线的铜层进行后清洗处理。 后清洗过程包括使用基于柠檬酸的化学品进行初级化学清洗。 然后在使用抗坏血酸的化学品进行了主要化学清洗的铜层上进行二次化学清洗。 在完成后清洗处理之后，防止了铜离子随时间的迁移，从而提高了半导体器件的可靠性。

公开(公告)号：US20080242084A1

公开(公告)日：2008-10-02

申请号：US11939631

申请日：2007-11-14

申请人： Hyung Hwan KIM ,  Jong Goo JUNG

发明人： Hyung Hwan KIM ,  Jong Goo JUNG

IPC分类号： H01L21/4763

CPC分类号： H01L21/76819 ,  H01L27/10894

摘要： In a method for planarizing an insulation layer in a semiconductor device, an insulation layer is formed over a semiconductor substrate having a cell region and a peripheral region. The cell region is higher than the peripheral region due to a capacitor formed in the cell region. A metal layer is formed over the insulation layer. The metal layer is chemical mechanical polished to expose the insulation layer portion in the cell region. The exposed insulation layer portion in the cell region is chemical mechanical polishing to planarize the insulation layer, and the planarized insulation layer and the remaining metal layer are chemical mechanical polishing to remove the metal layer remained in the peripheral region. The method for planarizing an insulation layer does not require a separate photosensitive layer forming process or a dry etching process.

摘要翻译： 在半导体装置中的绝缘层平坦化的方法中，在具有单元区域和周边区域的半导体基板上形成绝缘层。 由于在电池区域形成的电容器，电池区域比外围区域高。 在绝缘层上形成金属层。 金属层被化学机械抛光以暴露电池区域中的绝缘层部分。 电池区域中的露出的绝缘层部分是化学机械抛光以使绝缘层平坦化，并且平坦化的绝缘层和剩余的金属层是化学机械抛光以去除留在周边区域中的金属层。 用于平坦化绝缘层的方法不需要单独的感光层形成工艺或干蚀刻工艺。