发明申请
US20080258765A1 Low-power transceiver architectures for programmable logic integrated circuit devices 有权
用于可编程逻辑集成电路器件的低功耗收发器架构

Low-power transceiver architectures for programmable logic integrated circuit devices
摘要:
High-speed serial interface or transceiver circuitry on a programmable logic device integrated circuit (“PLD”) includes features that permit the PLD to satisfy a wide range of possible user needs or applications. This range includes both high-performance applications and applications in which reduced power consumption by the PLD is important. In the latter case, any one or more of various features can be used to help reduce power consumption.
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