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    Multi-purpose phase-locked loop for low cost transceiver
    1.
    发明授权
    Multi-purpose phase-locked loop for low cost transceiver 有权
    用于低成本收发器的多功能锁相环

    公开(公告)号：US08619931B1

    公开(公告)日：2013-12-31

    申请号：US12622152

    申请日：2009-11-19

    申请人： Tien Duc Pham ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Vinh Van Ho ,  Leon Zheng

    发明人： Tien Duc Pham ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Vinh Van Ho ,  Leon Zheng

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0337 ,  H04L7/002

    摘要： Integrated circuits having transceivers capable of high-speed (e.g., 1 Gbps) operation without dedicated phase-locked loop circuitry are provided. One such integrated circuit device may include one or more transceivers capable of transmitting and receiving serial signals of approximately 1 Gbps or greater, and a multi-purpose phase-locked loop capable of providing a multi-phase clock signal to the one or more transceivers.

    摘要翻译： 提供了具有能够在没有专用锁相环电路的情况下能够进行高速（例如，1Gbps）操作的收发器的集成电路。 一个这样的集成电路设备可以包括能够发送和接收大约1Gbps或更大的串行信号的一个或多个收发器，以及能够向一个或多个收发器提供多相时钟信号的多用途锁相环。

    Apparatus and methods for low-jitter transceiver clocking
    2.
    发明授权
    Apparatus and methods for low-jitter transceiver clocking 有权
    低抖动收发器时钟的装置和方法

    公开(公告)号：US08406258B1

    公开(公告)日：2013-03-26

    申请号：US12752984

    申请日：2010-04-01

    申请人： Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Sergey Shumarayev ,  Allen Chan

    发明人： Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Sergey Shumarayev ,  Allen Chan

    IPC分类号： H04J3/06

    CPC分类号： H03M9/00 ,  H03K19/1776 ,  H04J3/047 ,  H04J3/0685

    摘要： One embodiment relates to an integrated circuit which includes multiple communication channels, a clock multiplexer in each channel, two low-jitter clock generator circuits, and clock distribution circuitry. Each channel includes circuitry arranged to communicate a serial data stream using a reference clock signal, and the clock multiplexer in each channel is configured to select the reference clock signal from a plurality of input clock signals. The first low-jitter clock generator circuit is arranged to generate a first clock signal using a first inductor-capacitor-based oscillator circuit, and the second low-jitter clock generator circuit is arranged to generate a second clock signal using a second inductor-capacitor-based oscillator circuit The first and second inductor-capacitor-based oscillator circuits have different tuning ranges. The clock distribution circuitry is arranged to input the first and second low-jitter clock signals to each said clock multiplexer. Other embodiments and features are also disclosed.

    摘要翻译： 一个实施例涉及一种集成电路，其包括多个通信信道，每个信道中的时钟多路复用器，两个低抖动时钟发生器电路和时钟分配电路。 每个通道包括被布置为使用参考时钟信号传送串行数据流的电路，并且每个通道中的时钟复用器被配置为从多个输入时钟信号中选择参考时钟信号。 第一低抖动时钟发生器电路被布置为使用第一基于电感器 - 电容器的振荡器电路产生第一时钟信号，并且第二低抖动时钟发生器电路被布置为使用第二电感器电容器产生第二时钟信号 基振荡电路基于第一和第二电感电容器的振荡电路具有不同的调谐范围。 时钟分配电路被布置为将第一和第二低抖动时钟信号输入到每个所述时钟多路复用器。 还公开了其它实施例和特征。

    SIMULATION TOOL FOR HIGH-SPEED COMMUNICATIONS LINKS
    3.
    发明申请
    SIMULATION TOOL FOR HIGH-SPEED COMMUNICATIONS LINKS 有权
    高速通信链接的仿真工具

    公开(公告)号：US20110257953A1

    公开(公告)日：2011-10-20

    申请号：US12762848

    申请日：2010-04-19

    申请人： Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

    发明人： Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5009 ,  G06F17/5036 ,  G06F2217/10

    摘要： A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

    摘要翻译： 提供了一种用于模拟高速通信链路系统的链路仿真工具。 通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。 链接仿真工具可以使用行为模型对每个子系统进行建模。 行为模型可以包括特征功能，例如传递函数，概率密度函数和眼睛特征。 链路仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎 的链接系统。 链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。

    SIGNAL LOSS DETECTOR FOR HIGH-SPEED SERIAL INTERFACE OF A PROGRAMMABLE LOGIC DEVICE
    4.
    发明申请
    SIGNAL LOSS DETECTOR FOR HIGH-SPEED SERIAL INTERFACE OF A PROGRAMMABLE LOGIC DEVICE 有权
    用于可编程逻辑器件高速串行接口的信号丢失检测器

    公开(公告)号：US20110235756A1

    公开(公告)日：2011-09-29

    申请号：US13151717

    申请日：2011-06-02

    申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

    发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

    IPC分类号： H04L27/06

    CPC分类号： H04L25/45

    摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

    摘要翻译： 信号丢失检测器包括对输入数据进行数字和模拟监测。 输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。 如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

    Power supply filtering for programmable logic device having heterogeneous serial interface architecture
    5.
    发明授权
    Power supply filtering for programmable logic device having heterogeneous serial interface architecture 有权
    具有异构串行接口架构的可编程逻辑器件的电源滤波

    公开(公告)号：US07903679B1

    公开(公告)日：2011-03-08

    申请号：US11622396

    申请日：2007-01-11

    申请人： Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

    发明人： Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

    IPC分类号： H04L12/56

    CPC分类号： H03K19/17744

    摘要： In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.

    摘要翻译： 在具有多种不同类型的串行接口的可编程逻辑器件中，不同的电源滤波方案被应用于不同的接口。 对于以最低数据速率操作的接口，例如，可以提供包括一个或多个去耦电容器的1Gbps电路板电平滤波器。 对于以较高数据速率工作的接口，例如，也可以提供3 Gbps适度的封装内滤波，这可能包括功率岛解耦。 对于以更高的数据速率运行的接口，例如，也可以提供包括一个或多个封装内去耦电容器的6Gbps更实质的封装内滤波。 对于以最高数据速率工作的接口，例如，可以提供10Gbps片上滤波，其可以包括一个或多个片上滤波或调节网络。 片上调节器可以可编程地旁路，允许用户权衡功能以节省功率。

    Programmable logic device transceiver architectures that facilitate using various numbers of transceiver channels together
    6.
    发明授权
    Programmable logic device transceiver architectures that facilitate using various numbers of transceiver channels together 有权
    可编程逻辑器件收发器架构，便于将各种数量的收发器通道一起使用

    公开(公告)号：US07812634B1

    公开(公告)日：2010-10-12

    申请号：US11726471

    申请日：2007-03-21

    申请人： Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang

    发明人： Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

    摘要： Transceiver circuitry on a programmable logic device integrated circuit (“PLD”) is preferably provided in a plurality of identical or at least similar modules. Each module preferably includes a plurality of transceiver channels and a clock source unit. Clock distribution circuitry is provided for distributing the signal of a module's clock source to all of the transceiver channels in that module, and also selectively beyond that module to other modules.

    摘要翻译： 可编程逻辑器件集成电路（“PLD”）上的收发器电路优选地设置在多个相同或至少相似的模块中。 每个模块优选地包括多个收发器通道和时钟源单元。 提供时钟分配电路用于将模块的时钟源的信号分配给该模块中的所有收发器通道，并且还选择性地超出该模块到其他模块。

    Integrated circuit architectures with heterogeneous high-speed serial interface circuitry
    7.
    发明授权
    Integrated circuit architectures with heterogeneous high-speed serial interface circuitry 有权
    具有异构高速串行接口电路的集成电路架构

    公开(公告)号：US07759972B1

    公开(公告)日：2010-07-20

    申请号：US11981934

    申请日：2007-10-31

    申请人： Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding ,  Thungoc M. Tran ,  Tim Tri Hoang

    发明人： Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding ,  Thungoc M. Tran ,  Tim Tri Hoang

    IPC分类号： H01L25/00

    CPC分类号： H03K19/177

    摘要： An integrated circuit device such as a programmable logic device (“PLD”) includes a plurality of blocks of legacy circuitry. These legacy blocks leave at least one corner of the device unoccupied by such legacy circuitry. This at least one corner is used for relatively newly developed circuitry so as to simplify and speed the design of relatively new circuitry, to avoid having to significantly redesign any of the legacy circuitry to give the device the capabilities of the new circuitry, etc. The relatively newly developed circuitry may be high-speed serial data signal interface (“HSSI”) circuitry that is capable of operating at serial data rates faster than any legacy HSSI circuitry on the device.

    摘要翻译： 诸如可编程逻辑器件（“PLD”）的集成电路器件包括多个遗留电路块。 这些传统块离开设备的至少一个角落，不被这种遗留电路占用。 这个至少一个角用于相对新开发的电路，以便简化和加速相对新的电路的设计，以避免必须重新设计任何传统电路以给予设备新电路的能力等。 相对新开发的电路可以是高速串行数据信号接口（“HSSI”）电路，其能够以比设备上的任何传统HSSI电路更快的串行数据速率工作。

    Signal amplitude detection circuitry without pattern dependencies for high-speed serial links
    8.
    发明授权
    Signal amplitude detection circuitry without pattern dependencies for high-speed serial links 有权
    信号幅度检测电路，无高速串行链路的模式相关性

    公开(公告)号：US07576570B1

    公开(公告)日：2009-08-18

    申请号：US11508607

    申请日：2006-08-22

    申请人： Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

    发明人： Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

    IPC分类号： H03K5/153

    CPC分类号： H03K5/153 ,  H03K5/24

    摘要： Precision amplitude detection circuitry without pattern dependencies is provided that includes rectifier circuitry to output a rectified voltage signal and delay circuitry to send one or more delayed or phase-shifted versions of a differential signal input to the rectifier circuitry. The delayed versions of the differential signal input may be delayed in order to reduce or eliminate the dips in the input seen by the rectifier. This may help correct for low rectified voltage levels. The signal amplitude detection circuitry of the present invention may be incorporated on the input pin of any programmable logic resource and may be included in communication circuitry of a PLD. The precision amplitude detection circuitry may operate in the Gbps (gigabit per second) range.

    摘要翻译： 提供了没有图形相关性的精密幅度检测电路，其包括整流电路，用于输出整流电压信号和延迟电路，以将一个或多个差分信号输入的延迟或相移版本发送到整流器电路。 可以延迟差分信号输入的延迟版本，以便减少或消除由整流器看到的输入中的下降。 这可能有助于校正低整流电压电平。 本发明的信号幅度检测电路可以结合在任何可编程逻辑资源的输入引脚上，并且可以被包括在PLD的通信电路中。 精度幅度检测电路可以以Gbps（千兆位/秒）范围工作。

    Simulation tool for high-speed communications links
    9.
    发明授权
    Simulation tool for high-speed communications links 有权
    用于高速通信链接的仿真工具

    公开(公告)号：US08626474B2

    公开(公告)日：2014-01-07

    申请号：US12762848

    申请日：2010-04-19

    申请人： Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

    发明人： Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

    IPC分类号： G06F7/60 ,  G06G7/62 ,  G06F17/50

    CPC分类号： G06F17/5009 ,  G06F17/5036 ,  G06F2217/10

    摘要： A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

    摘要翻译： 提供了一种用于模拟高速通信链路系统的链路仿真工具。 通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。 链接仿真工具可以使用行为模型对每个子系统进行建模。 行为模型可以包括特征功能，例如传递函数，概率密度函数和眼睛特征。 链路仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎 的链接系统。 链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。

    Adaptation circuitry and methods for decision feedback equalizers
    10.
    发明授权
    Adaptation circuitry and methods for decision feedback equalizers 有权
    用于判决反馈均衡器的适应电路和方法

    公开(公告)号：US08391350B2

    公开(公告)日：2013-03-05

    申请号：US12875703

    申请日：2010-09-03

    申请人： Doris Po Ching Chan ,  Thungoc M. Tran

    发明人： Doris Po Ching Chan ,  Thungoc M. Tran

    IPC分类号： H03K5/159

    CPC分类号： H04L25/03057 ,  H04L25/03885 ,  H04L2025/0349 ,  H04L2025/03636

    摘要： Decision feedback equalizer (“DFE”) circuitry bases determination of the coefficients that are used in its various taps on the algebraic sign of the current value of an error signal and prior serial data signal values output by the DFE circuitry. Use of such algebraic sign information (rather than full error signal values) greatly simplifies the circuitry needed to determine the tap coefficients. The DFE circuitry can be adaptive, i.e., such that it automatically adjusts the tap coefficients for changing serial data signal transmission conditions.

    摘要翻译： 判决反馈均衡器（DFE）电路用于确定在各种抽头中使用的系数，该误差信号的当前值的代数符号和DFE电路输出的先前的串行数据信号值。 使用这种代数符号信息（而不是全错误信号值）大大简化了确定抽头系数所需的电路。 DFE电路可以是自适应的，即，其自动调整抽头系数以改变串行数据信号传输条件。