发明申请
- 专利标题： POST LAST WIRING LEVEL INDUCTOR USING PATTERNED PLATE PROCESS
- 专利标题（中）： 使用图案板过程的最后接线电平
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申请号： US12174020申请日： 2008-07-16
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公开(公告)号： US20080277759A1公开(公告)日： 2008-11-13
- 发明人: Anil Kumar Chinthakindi , Douglas Duane Coolbaugh , John Edward Florkey , Jeffrey Peter Gambino , Zhong-Xiang He , Anthony Kendall Stamper , Kunal Vaed
- 申请人： Anil Kumar Chinthakindi , Douglas Duane Coolbaugh , John Edward Florkey , Jeffrey Peter Gambino , Zhong-Xiang He , Anthony Kendall Stamper , Kunal Vaed
- 主分类号： H01L29/00
- IPC分类号： H01L29/00
摘要：
A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above a top surface of the substrate; an insulative layer on and above a top surface of the capping layer; an inductor comprising a first portion in and above the insulative layer and a second portion only above the insulative layer; and a wire bond pad within the insulative layer, wherein the first portion the inductor has a height in a first direction greater than a height of the wire bond pad in the first direction, wherein the first direction is perpendicularly directed from the top surface of substrate toward the insulative layer.
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