公开(公告)号：US07910450B2

公开(公告)日：2011-03-22

申请号：US11276282

申请日：2006-02-22

Applicant: Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  John E. Florkey ,  Heidi L. Greer ,  Robert M. Rassel ,  Anthony K. Stamper ,  Kunal Vaed

Inventor： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  John E. Florkey ,  Heidi L. Greer ,  Robert M. Rassel ,  Anthony K. Stamper ,  Kunal Vaed

IPC: H01L21/20

CPC classification number: H01L29/8605 ,  H01L27/0802 ,  H01L28/20

Abstract: The present invention provides a semiconductor structure including a buried resistor with improved control, in which the resistor is fabricated in a region of a semiconductor substrate beneath a well region that is also present in the substrate. In accordance with the present invention, the inventive structure includes a semiconductor substrate containing at least a well region; and a buried resistor located in a region of the semiconductor substrate that is beneath said well region. The present invention also provides a method of fabricating such a structure in which a deep ion implantation process is used to form the buried resistor and a shallower ion implantation process is used in forming the well region.

Abstract translation: 本发明提供一种包括具有改进控制的掩埋电阻器的半导体结构，其中电阻器制造在半导体衬底的也存在于衬底中的阱区域下方的区域中。 根据本发明，本发明的结构包括至少含有一个阱区的半导体衬底; 以及位于半导体衬底的位于所述阱区之下的区域中的掩埋电阻器。 本发明还提供一种制造这样的结构的方法，其中使用深离子注入工艺来形成掩埋电阻器，并且在形成阱区域中使用较浅的离子注入工艺。

公开(公告)号：US07662722B2

公开(公告)日：2010-02-16

申请号：US11626548

申请日：2007-01-24

Applicant: Anthony K. Stamper ,  Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  William J. Murphy ,  Kunal Vaed

Inventor： Anthony K. Stamper ,  Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  William J. Murphy ,  Kunal Vaed

IPC: H01L21/302

CPC classification number: H01L27/0688 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/53295 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic chip, and a plurality of stacked interlevel dielectric (“ILD”) layers are formed to overlie the plurality of FEOL devices, the plurality of stacked ILD layers including a first ILD layer and a second ILD layer, where the second ILD layer is resistant to attack by a first etchant which attacks the first ILD layer. A passive device is formed to overlie at least the first ILD layer. Using the first etchant, a portion of the first ILD layer in registration with the passive device is removed to form an air gap which underlies the passive device in registration with the passive device.

Abstract translation: 提供了一种用于制造微电子芯片的方法，该微电子芯片包括覆盖气隙的诸如电感器的无源器件。 在这种方法中，在微电子芯片的半导体区域中形成多个前端（“FEOL”）器件，并且形成多个层叠的层间电介质（“ILD”）层以覆盖多个 的多个层叠的ILD层，包括第一ILD层和第二ILD层，其中第二ILD层抵抗攻击第一ILD层的第一蚀刻剂的侵袭。 形成无源器件至少覆盖第一ILD层。 使用第一蚀刻剂，除去与无源器件对准的第一ILD层的一部分，以形成与被动器件对准的无源器件下方的气隙。

公开(公告)号：US07545007B2

公开(公告)日：2009-06-09

申请号：US11161533

申请日：2005-08-08

Applicant: Heidi L. Greer ,  Seong-Dong Kim ,  Robert M. Rassel ,  Kunal Vaed

Inventor： Heidi L. Greer ,  Seong-Dong Kim ,  Robert M. Rassel ,  Kunal Vaed

IPC: H01L29/76

CPC classification number: H01L29/93 ,  H01L27/0811 ,  H01L29/36 ,  H01L29/94

Abstract: A MOS varactor is formed having a gate electrode comprising at least two abutting oppositely doped regions shorted together, in which the two regions are implanted simultaneously with source/drain implants for first and second types of transistor; at least one contact to a lower electrode is also formed simultaneously with the source/drain implants for the first type of transistor; the varactor insulator is formed simultaneously with the gate insulator for one type of transistor; and the lower electrode is formed simultaneously with a well for the first type of transistor, so that no additional mask is required.

Abstract translation: 形成MOS变容二极管，其栅极电极包括至少两个彼此短接的邻接的相对掺杂区域，其中两个区域与用于第一和第二类型晶体管的源极/漏极注入同时注入; 与第一类型的晶体管的源极/漏极注入同时形成与下部电极的至少一个接触; 变容二极管与栅绝缘体同时形成一种晶体管; 并且下电极与用于第一类型晶体管的阱同时形成，使得不需要附加掩模。

公开(公告)号：US20080293233A1

公开(公告)日：2008-11-27

申请号：US12170464

申请日：2008-07-10

Applicant: Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

Inventor： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC: H01L21/44

CPC classification number: H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of a semiconductor device. A substrate is provided. At least one metal wiring level is within the substrate. An insulative layer is deposited on a surface of the substrate. An inductor is formed within the insulative layer using a patterned plate process. A wire bond pad is formed within the insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

Abstract translation: 一种半导体器件的方法。 提供基板。 衬底内至少有一个金属布线层。 绝缘层沉积在衬底的表面上。 使用图案化板工艺在绝缘层内形成电感器。 在绝缘层内形成引线接合焊盘，其中引线接合焊盘的至少一部分与电感器基本上共面。

公开(公告)号：US07410894B2

公开(公告)日：2008-08-12

申请号：US11161217

申请日：2005-07-27

Applicant: Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John E. Florkey ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Kunal Vaed

Inventor： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John E. Florkey ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Kunal Vaed

IPC: H01L21/44 ,  H01L21/20 ,  H01L29/00

CPC classification number: H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure, and the semiconductor structure so formed, wherein a transmission line, such as an inductor, is formed on a planar level above the surface of a last metal wiring level.

Abstract translation: 一种形成半导体结构的方法以及如此形成的半导体结构，其中诸如电感器的传输线形成在最后一个金属布线层的表面上方的平面上。

公开(公告)号：US07354872B2

公开(公告)日：2008-04-08

申请号：US10908789

申请日：2005-05-26

Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Kenneth J. Stein ,  Kunal Vaed

Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Kenneth J. Stein ,  Kunal Vaed

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/02181 ,  C23C16/405 ,  C23C16/45523 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02189 ,  H01L21/28194 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/517

Abstract: Methods of forming a high dielectric constant dielectric layer are disclosed including providing a process chamber including a holder for supporting a substrate, introducing a first gas comprising a high dielectric constant (Hi-K) dielectric precursor and an oxygen (O2) oxidant into the process chamber to form a first portion of the high dielectric constant dielectric layer on the substrate, and switching from a flow of the first gas to a flow of a second gas comprising the Hi-K dielectric precursor and an ozone (O3) oxidant to form a second portion of the high dielectric constant dielectric layer on the first portion. In an alternative embodiment, another portion can be formed on the second portion using the oxygen oxidant. The invention increases throughput by at least 20% without reliability or leakage degradation and without the need for additional equipment.

Abstract translation: 公开了形成高介电常数电介质层的方法，包括提供包括用于支撑衬底的保持器的处理室，引入包含高介电常数（Hi-K）电介质前体和氧（O 2） / SUB>）氧化剂进入处理室以形成衬底上的高介电常数电介质层的第一部分，并且从第一气体的流动切换到包括Hi-K电介质前体的第二气体的流动，以及 臭氧（O 3 3）氧化剂以形成第一部分上的高介电常数介电层的第二部分。 在替代实施例中，可以使用氧氧化剂在第二部分上形成另一部分。 本发明将产量提高了至少20％，而没有可靠性或泄漏降级，并且不需要额外的设备。

公开(公告)号：US07732294B2

公开(公告)日：2010-06-08

申请号：US12170464

申请日：2008-07-10

Applicant: Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

Inventor： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC: H01L21/20

CPC classification number: H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of a semiconductor device. A substrate is provided. At least one metal wiring level is within the substrate. An insulative layer is deposited on a surface of the substrate. An inductor is formed within the insulative layer using a patterned plate process. A wire bond pad is formed within the insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

Abstract translation: 一种半导体器件的方法。 提供基板。 衬底内至少有一个金属布线层。 绝缘层沉积在衬底的表面上。 使用图案化板工艺在绝缘层内形成电感器。 在绝缘层内形成引线接合焊盘，其中引线接合焊盘的至少一部分与电感器基本上共面。

公开(公告)号：US07608909B2

公开(公告)日：2009-10-27

申请号：US11164765

申请日：2005-12-05

Applicant: Anil K. Chinthakindi ,  Robert A. Groves ,  Youri V. Tretiakov ,  Kunal Vaed ,  Richard P. Volant

Inventor： Anil K. Chinthakindi ,  Robert A. Groves ,  Youri V. Tretiakov ,  Kunal Vaed ,  Richard P. Volant

IPC: H01L21/76

CPC classification number: H01P11/003 ,  H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/53238 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the interlevel dielectric layer. A signal transmission line is formed in a second metallization level formed over the interlevel dielectric layer, the signal transmission line being disposed over the sacrificial material. A portion of dielectric material included within the second metallization level is removed so as to expose the sacrificial material, wherein a portion of the sacrificial material is exposed through a plurality of access holes formed through the signal transmission line. The sacrificial material is removed so as to create an air gap beneath the signal transmission line.

Abstract translation: 用于形成用于半导体器件的传输线结构的方法包括在第一金属化层上形成层间电介质层，去除层间电介质层的一部分，并在通过去除部分的部分产生的一个或多个空隙内形成牺牲材料 层间电介质层。 信号传输线形成在层间电介质层上形成的第二金属化层，信号传输线设置在牺牲材料之上。 包括在第二金属化水平内的电介质材料的一部分被去除以暴露牺牲材料，其中牺牲材料的一部分通过穿过信号传输线形成的多个访问孔而露出。 去除牺牲材料，以在信号传输线下方产生气隙。

公开(公告)号：US20080173981A1

公开(公告)日：2008-07-24

申请号：US11624712

申请日：2007-01-19

Applicant: Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Kunal Vaed

Inventor： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Kunal Vaed

IPC: H01L27/06 ,  H01L21/02

CPC classification number: H01L28/91 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An Integrated Circuit (IC) chip with one or more vertical plate capacitors, each vertical plate capacitor connected to circuits on the IC chip and a method of making the chip capacitors. The vertical plate capacitors are formed with base plate pattern (e.g., damascene copper) on a circuit layer and at least one upper plate layer (e.g., dual damascene copper) above, connected to and substantially identical with the base plate pattern. A vertical pair of capacitor plates are formed by the plate layer and base plate. Capacitor dielectric between the vertical pair of capacitor plates is, at least in part, a high-k dielectric.

Abstract translation: 具有一个或多个垂直板电容器的集成电路（IC）芯片，每个垂直板电容器连接到IC芯片上的电路和制造芯片电容器的方法。 垂直板电容器在电路层上形成有底板图案（例如，镶嵌铜），以及与基板图案连接并基本相同的至少一个上板层（例如双镶嵌铜）。 一对电容器板由板层和底板形成。 垂直对电容器板之间的电容电介质至少部分地是高k电介质。

公开(公告)号：US20080122574A1

公开(公告)日：2008-05-29

申请号：US11458494

申请日：2006-07-19

Applicant: Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  John E. Florkey ,  Robert M. Rassel ,  Kunal Vaed

Inventor： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  John E. Florkey ,  Robert M. Rassel ,  Kunal Vaed

IPC: H01C1/06 ,  H01L21/20

CPC classification number: H01L27/0802 ,  H01L21/26513 ,  H01L28/20

Abstract: A polysilicon containing resistor includes: (1) a p dopant selected from the group consisting of boron and boron difluoride; and (2) an n dopant selected from the group consisting of arsenic and phosphorus. Each of the p dopant and the n dopant has a dopant concentration from about 1e18 to about 1e21 dopant atoms per cubic centimeter. A method for forming the polysilicon resistor uses corresponding implant doses from about 1e14 to about 1e16 dopant ions per square centimeter. The p dopant and the n dopant may be provided simultaneously or sequentially. The method provides certain polysilicon resistors with a sheet resistance percentage standard deviation of less than about 1.5%, for a polysilicon resistor having a sheet resistance from about 100 to about 5000 ohms per square.

Abstract translation: 含多晶硅的电阻器包括：（1）选自硼和二氟化硼的p掺杂剂; 和（2）选自砷和磷的n掺杂剂。 p掺杂剂和n掺杂剂中的每一个掺杂剂的掺杂剂浓度从每立方厘米约1e18至约1e21掺杂剂原子。 用于形成多晶硅电阻器的方法使用相对于每平方厘米约1e14至约1e16掺杂剂离子的注入剂量。 p掺杂剂和n掺杂剂可以同时或顺序地提供。 对于具有约100至约5000欧姆/平方的薄层电阻的多晶硅电阻器，该方法提供某些多晶硅电阻器的薄层电阻百分比标准偏差小于约1.5％。