- 专利标题： Semiconductor integrated circuit capable of testing with small scale circuit configuration
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申请号： US12219230申请日： 2008-07-17
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公开(公告)号： US20080288836A1公开(公告)日： 2008-11-20
- 发明人: Soichi Kobayashi , Yoshiaki Yamazaki , Yukihiko Shimazu
- 申请人： Soichi Kobayashi , Yoshiaki Yamazaki , Yukihiko Shimazu
- 申请人地址： JP Chiyoda-ku
- 专利权人： RENESAS TECHNOLOGY CORP.
- 当前专利权人： RENESAS TECHNOLOGY CORP.
- 当前专利权人地址： JP Chiyoda-ku
- 优先权： JP2003-073951 20030318
- 主分类号： G11C29/00
- IPC分类号： G11C29/00 ; G06F11/277
摘要：
In a test mode, a comparator compares for each column a value of data read from each memory cell connected to an activated word line with an expected value to be read from each memory cell. An error register holds error data based on a comparison result by a comparator. Each bit of the error data indicates the comparison result by the comparator for a corresponding column. Each bit is set to “0” when the comparison result for the corresponding column always indicates equality whichever word line is activated, and is set to “1” when once the comparison result for the corresponding column indicates difference.