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32 条记录 (耗时 0.016 秒)

    Semiconductor integrated circuit with self-test function
    3.
    发明授权
    Semiconductor integrated circuit with self-test function 失效
    具有自检功能的半导体集成电路

    公开(公告)号：US5051997A

    公开(公告)日：1991-09-24

    申请号：US622316

    申请日：1990-12-03

    申请人： Narumi Sakashita ,  Yukihiko Shimazu

    发明人： Narumi Sakashita ,  Yukihiko Shimazu

    IPC分类号： G01R31/28 ,  G06F11/27 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04

    CPC分类号： G06F11/27

    摘要： Apparatus is disclosed for a self-test function internal to a semiconductor integrated circuit. The invention includes an internal random number generator for generating test data for use by a self-test program. As a result of the invention, external equipment is not necessary for executing the self-test, internal memory for storing for self-test data can be decreased, and self-test can be performed readily by the user. Furthermore, since self-test result data is compressed so as to be compared with the data of prediction values, the data of the test result can be reduced for easy processing.

    摘要翻译： 公开了用于半导体集成电路内部的自检功能的装置。 本发明包括一个内部随机数发生器，用于产生用于自检程序的测试数据。 作为本发明的结果，外部设备不需要执行自检，可以减少用于自检数据的存储的内部存储器，并且用户可以容易地进行自检。 此外，由于自检结果数据被压缩以便与预测值的数据进行比较，因此可以减少测试结果的数据以便于处理。

    Coded incrementer having minimal carry propagation delay
    4.
    发明授权
    Coded incrementer having minimal carry propagation delay 失效
    具有最小进位传播延迟的编码增量器

    公开(公告)号：US4914616A

    公开(公告)日：1990-04-03

    申请号：US131864

    申请日：1987-12-11

    申请人： Taketora Shiraishi ,  Yukihiko Shimazu

    发明人： Taketora Shiraishi ,  Yukihiko Shimazu

    IPC分类号： G06F7/50 ,  G06F7/505 ,  G06F7/506

    CPC分类号： G06F7/5055

    摘要： As the incrementer of the invention comprises a shift register for its lower order bits, while its higher bit portions are constructed in the same way as a conventional incrementer, the incrementer can give output signals directly to a memory and the like without the necessity of decoding the same, and the incrementer is free from carry propagation delay possibilities, which assures an improved rate of operation of the incrementer as a whole.

    摘要翻译： 由于本发明的增量器包括用于其较低阶位的移位寄存器，而其较高位部分以与常规增量器相同的方式构造，所以递增器可以将输出信号直接提供给存储器等而不需要解码 相同，并且增量器没有进位传播延迟的可能性，这保证了整体上增量器的操作速率的提高。

    Semiconductor memory device having initialization transistor
    5.
    发明授权
    Semiconductor memory device having initialization transistor 失效
    具有初始晶体管的半导体存储器

    公开(公告)号：US4777623A

    公开(公告)日：1988-10-11

    申请号：US869653

    申请日：1986-06-02

    申请人： Yukihiko Shimazu ,  Eiichi Teraoka

    发明人： Yukihiko Shimazu ,  Eiichi Teraoka

    IPC分类号： G11C7/00 ,  G06F1/24 ,  G11C11/401 ,  G11C11/41 ,  H03K3/037 ,  H03K3/356 ,  G11C11/40

    CPC分类号： H03K3/356095 ,  H03K3/35606

    摘要： A memory circuit 14 comprises a MOS transistor 15 having its threshold voltage selected to be higher than the output voltage on the occasion of the ordinary operation. Consequently, the MOS transistor 15 is off on the occasion of the ordinary operation, and a ratio latch 4 performs the ordinary storing operation. Meanwhile, if the output voltage of the power source 12 is raised, the MOS transistor 15 turns on to pull down the potential of a data input line 6a to the ratio latch. Accordingly, the ratio latch 4 is forced to be set.

    摘要翻译： 存储电路14包括在正常操作时选择其阈值电压高于输出电压的MOS晶体管15。 因此，在正常工作的情况下，MOS晶体管15截止，比例锁存器4进行普通存储操作。 同时，如果电源12的输出电压升高，则MOS晶体管15导通，将数据输入线6a的电位下拉到比率锁存器。 因此，比例闩锁4被强制设定。

    Clock system implementing divided power supply wiring
    6.
    发明授权
    Clock system implementing divided power supply wiring 失效
    时钟系统实现分电源接线

    公开(公告)号：US5122693A

    公开(公告)日：1992-06-16

    申请号：US613187

    申请日：1990-11-13

    申请人： Nobuhiko Honda ,  Toyohiko Yoshida ,  Yukihiko Shimazu

    发明人： Nobuhiko Honda ,  Toyohiko Yoshida ,  Yukihiko Shimazu

    IPC分类号： G06F1/10 ,  H01L21/822 ,  H01L27/04 ,  H03K5/00

    CPC分类号： G06F1/10

    摘要： Integrated circuits in which a phase difference between the external and internal clocks can be reduced by decreasing transistor stages from the input of an external clock to the output of an internal clock drive stages and also noise can be reduced which is generated when the clock driver drives at a high speed the internal clock having a heavy load and the noise can be prevented from propagation to other portions to avoid having a bad effect on other circuits, and further the internal clock having the same phase can be supplied to each part of the chip even at a high operating frequency by minimizing skew of the internal clock signal on the chip and still further a demand current can be reduced by eliminating a passing current of the internal clock signal driver.

    摘要翻译： 可以通过将晶体管级从外部时钟的输入减少到内部时钟驱动级的输出而减小外部和内部时钟之间的相位差的集成电路，并且还可以减少当时钟驱动器驱动时产生的噪声 高速地，内部时钟具有较大的负载，并且可以防止噪声传播到其它部分，以避免对其他电路造成不良影响，此外，具有相同相位的内部时钟可以提供给芯片的每个部分 即使在高工作频率下，通过最小化芯片上的内部时钟信号的偏移，并且还可以通过消除内部时钟信号驱动器的通过电流来降低需求电流。

    Comparator circuit
    7.
    发明授权
    Comparator circuit 失效
    比较器电路

    公开(公告)号：US4903005A

    公开(公告)日：1990-02-20

    申请号：US250461

    申请日：1988-09-28

    申请人： Narumi Sakashita ,  Yukihiko Shimazu

    发明人： Narumi Sakashita ,  Yukihiko Shimazu

    IPC分类号： G06F7/02

    CPC分类号： G06F7/026

    摘要： A multiple digit comparator checks the first and the second input data for a match. If the two input data match, the carry input data from the previous digit is outputted as the carry output data for the next digit; if the two input data do not match, then a no match signal is outputted as the carry output data for the next digit. Next, if the carry input data and the carry output data do not match then a change point signal is outputted. When this change point signal is outputted, the first and the second input data are outputted. This facilitates the design of a more regular comparator circuit layout and of a faster comparator circuit.

    摘要翻译： 多位数比较器检查第一和第二输入数据以进行匹配。 如果两个输入数据相匹配，则前一个数字的进位输入数据作为下一个数字的进位输出数据输出; 如果两个输入数据不匹配，则输出不匹配信号作为下个数字的进位输出数据。 接下来，如果进位输入数据和进位输出数据不匹配，则输出变化点信号。 当输出该变化点信号时，输出第一和第二输入数据。 这有助于设计更加规则的比较器电路布局和更快的比较器电路。

    Bus control circuit effecting timing control using cycle registers for respective cycles holding signal levels corresponding to bus control signals that are output by arrangement of signal level
    8.
    发明授权
    Bus control circuit effecting timing control using cycle registers for respective cycles holding signal levels corresponding to bus control signals that are output by arrangement of signal level 有权
    总线控制电路利用周期寄存器对周期寄存器进行定时控制，以保持对应于通过信号电平排列输出的总线控制信号的信号电平

    公开(公告)号：US06721897B1

    公开(公告)日：2004-04-13

    申请号：US09735496

    申请日：2000-12-14

    申请人： Akira Oizumi ,  Norio Masui ,  Yukihiko Shimazu

    发明人： Akira Oizumi ,  Norio Masui ,  Yukihiko Shimazu

    IPC分类号： G06F506

    CPC分类号： G06F13/4063

    摘要： A bus control circuit includes cycle registers provided with areas for holding signal levels of system-to-external bus control signals such that each of the cycle registers is provided for a corresponding cycle. A default register, additionally included in the bus control circuit, holds signal levels of the system-to-external bus control signals in a normal state. The signal levels of the system-to-external bus control signals held in the corresponding areas in the cycle registers are output cycle by cycle. When the normal state takes over, the signal levels held in the corresponding areas in the default register are output.

    摘要翻译： 总线控制电路包括设置有用于保持系统到外部总线控制信号的信号电平的区域的周期寄存器，使得每个周期寄存器被提供用于相应的周期。 额外包含在总线控制电路中的默认寄存器将系统到外部总线控制信号的信号电平保持在正常状态。 保持在循环寄存器中的相应区域中的系统到外部总线控制信号的信号电平逐周期输出。 当正常状态接管时，输出默认寄存器中相应区域中保持的信号电平。

    Serial data input circuit for the shifting-in of variable length data
    10.
    发明授权
    Serial data input circuit for the shifting-in of variable length data 失效
    串行数据输入电路，用于可变长度数据的移入

    公开(公告)号：US5195055A

    公开(公告)日：1993-03-16

    申请号：US833562

    申请日：1992-02-06

    申请人： Hisako Mizuoka ,  Yukihiko Shimazu

    发明人： Hisako Mizuoka ,  Yukihiko Shimazu

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1087 ,  G11C7/1078

    摘要： A serial data input circuit of this invention which, at the time of inputting of serial data, stores a predetermined signal represented in the bit outputted from the output side of the shift register when the last bit of serial data is inputted into the input side of a shift register and signals other than the predetermined signal in other bits respectively, so that, when all the bits of serial data are inputted into the shift register, the predetermined signal is outputted from the shift register, thereby realizing the circuit of small-sized, of simple in circuitry construction without a counter or the like.

    摘要翻译： 本发明的串行数据输入电路，在串行数据的输入时，存储在串行数据的最后位被输入到输入端的输入侧的从移位寄存器的输出侧输出的位中所表示的预定信号 移位寄存器和其他位中除了预定信号之外的信号，使得当串行数据的所有比特被输入到移位寄存器中时，从移位寄存器输出预定信号，从而实现小尺寸的电路 ，简单的电路结构，没有计数器等。