发明申请
- 专利标题： DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS
- 专利标题（中）： CMOS混合方向的双路隔离
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申请号： US12169991申请日： 2008-07-09
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公开(公告)号： US20080290379A1公开(公告)日： 2008-11-27
- 发明人: Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
- 申请人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
- 申请人地址： US NY Armonk
- 专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址： US NY Armonk
- 主分类号： H01L21/8234
- IPC分类号： H01L21/8234 ; H01L29/04
摘要：
The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
公开/授权文献
- US08097516B2 Dual trench isolation for CMOS with hybrid orientations 公开/授权日：2012-01-17
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