公开(公告)号：US07759772B2

公开(公告)日：2010-07-20

申请号：US11550681

申请日：2006-10-18

Applicant: Meikei Ieong ,  Devendra K. Sadana ,  Ghavam Shahidi

Inventor： Meikei Ieong ,  Devendra K. Sadana ,  Ghavam Shahidi

IPC: H01L29/04 ,  H01L31/036

CPC classification number: H01L21/76251 ,  H01L21/2007

Abstract: A method of forming a hybrid SOI substrate comprising an upper Si-containing layer and a lower Si-containing layer, wherein the upper Si-containing layer and the lower Si-containing layer have different crystallographic orientations. In accordance with the present invention, the buried insulating region may be located within one of the Si-containing layers or through an interface located between the two Si-containing layers.

Abstract translation: 一种形成包含上层含Si层和下层含Si层的混合SOI衬底的方法，其中上层含Si层和下层含Si层具有不同的结晶取向。 根据本发明，掩埋绝缘区域可以位于一个含硅层内或通过位于两个含Si层之间的界面。

公开(公告)号：US07713807B2

公开(公告)日：2010-05-11

申请号：US11958877

申请日：2007-12-18

Applicant: Bruce B. Doris ,  Kathryn W. Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Kern Rim ,  Jeffrey W. Sleight ,  Min Yang

Inventor： Bruce B. Doris ,  Kathryn W. Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Kern Rim ,  Jeffrey W. Sleight ,  Min Yang

IPC: H01L21/8238

CPC classification number: H01L21/76275 ,  H01L21/823807 ,  H01L21/84

Abstract: An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.

Abstract translation: 提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。 形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。 键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。 然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并将半导体材料重新生长在暴露表面上。 在平坦化之后，在第一器件区域中形成第一半导体器件，并且在再生长材料上形成第二半导体器件。

公开(公告)号：US20100112800A1

公开(公告)日：2010-05-06

申请号：US12683535

申请日：2010-01-07

Applicant: Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

Inventor： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

IPC: H01L21/28

CPC classification number: H01L21/28079 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/6659

Abstract: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

Abstract translation: 制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。 第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。 平坦化层位于第二栅极材料层上。 平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。 也可以在第一栅极叠层上形成蚀刻停止层。 所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。

公开(公告)号：US07619300B2

公开(公告)日：2009-11-17

申请号：US12434247

申请日：2009-05-01

Applicant: Meikei Ieong ,  Qiqing C. Ouyang

Inventor： Meikei Ieong ,  Qiqing C. Ouyang

IPC: H01L29/04

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7843

Abstract: The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having a second stressed semiconductor surface layer of a second crystallographic orientation located on a surface of a dielectric material. A trench isolation region is located between the first and second active area, and the trench isolation region is partially filled with a trench dielectric material and the dielectric material that is present underneath said second stressed semiconductor surface layer. The dielectric material within the trench isolation region has lower stress compared to that is used in conventional STI process and it is laterally abuts at least the second stressed semiconductor surface layer and extends to an upper surface of the trench isolation region.

Abstract translation: 本发明提供由混合取向的应力通道构成的半导体结构。 特别地，半导体结构包括第一有源区，其具有位于掩埋绝缘材料的表面上的第一晶体取向的第一应力半导体表面层和具有位于第二晶体取向的第二应力半导体表面层的第二有源区 在电介质材料的表面上。 沟槽隔离区域位于第一和第二有源区域之间，并且沟槽隔离区域部分地填充有沟槽电介质材料和位于所述第二应力半导体表面层下方的电介质材料。 与常规STI工艺中使用的沟槽隔离区域中的电介质材料相比具有较低的应力，并且它至少侧向邻接第二应力半导体表面层并且延伸到沟槽隔离区域的上表面。

公开(公告)号：US07605447B2

公开(公告)日：2009-10-20

申请号：US11162780

申请日：2005-09-22

Applicant: Bruce B. Doris ,  Gregory Costrini ,  Oleg Gluschenkov ,  Meikei Ieong ,  Nakgeuon Seong

Inventor： Bruce B. Doris ,  Gregory Costrini ,  Oleg Gluschenkov ,  Meikei Ieong ,  Nakgeuon Seong

IPC: H01L29/06 ,  H01L29/04 ,  H01L27/11

CPC classification number: H01L27/1104 ,  H01L27/11 ,  Y10S257/903 ,  Y10S438/973

Abstract: The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.

Abstract translation: 本发明涉及一种半导体器件结构，其包括在衬底中形成的至少一个SRAM单元。 这样的SRAM单元包括两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。 下拉晶体管和栅极晶体管在沟道宽度上基本相似，并且具有基本相似的源极 - 漏极掺杂浓度，而SRAM单元的β比率至少为1.5。 衬底优选地包括具有两个分离的区域集合的混合衬底，而这两组区域中的载流子迁移率以至少约1.5的因子差分。 更优选地，SRAM单元的下拉晶体管形成在一组区域中，并且栅极晶体管形成在另一组区域中，使得下拉晶体管中的电流大于 传输栅晶体管。

公开(公告)号：US07528056B2

公开(公告)日：2009-05-05

申请号：US11622543

申请日：2007-01-12

Applicant: Meikei Ieong ,  Douglas C. La Tulipe, Jr. ,  Leathen Shi ,  Anna W. Topol ,  James Vichiconti ,  Albert M. Young

Inventor： Meikei Ieong ,  Douglas C. La Tulipe, Jr. ,  Leathen Shi ,  Anna W. Topol ,  James Vichiconti ,  Albert M. Young

IPC: H01L21/36 ,  H01L21/20

CPC classification number: H01L21/02658 ,  H01L21/02667 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/78 ,  H01L29/7843

Abstract: A cost-effective and simple method of fabricating strained semiconductor-on-insulator (SSOI) structures which avoids epitaxial growth and subsequent wafer bonding processing steps is provided. In accordance with the present invention, a strain-memorization technique is used to create strained semiconductor regions on a SOI substrate. The transistors formed on the strained semiconductor regions have higher carrier mobility because the Si regions have been strained. The inventive method includes (i) ion implantation to create a thin amorphization layer, (ii) deposition of a high stress film on the amorphization layer, (iii) a thermal anneal to recrystallize the amorphization layer, and (iv) removal of the stress film. Because the SOI substrate was under stress during the recrystallization process, the final semiconductor layer will be under stress as well. The amount of stress and the polaity (tensile or compressive) of the stress can be controlled by the type and thickness of the stress films.

Abstract translation: 提供了一种制造应变绝缘体上半导体（SSOI）结构的成本有效和简单的方法，其避免了外延生长和随后的晶片接合处理步骤。 根据本发明，使用应变记忆技术在SOI衬底上产生应变半导体区域。 形成在应变半导体区域上的晶体管具有更高的载流子迁移率，因为Si区域已经变形。 本发明的方法包括（i）离子注入以产生薄的非晶化层，（ii）在非晶化层上沉积高应力膜，（iii）热退火以使非晶化层重结晶，和（iv）去除应力 电影。 由于在再结晶过程中SOI衬底处于应力状态，所以最终的半导体层也将受到应力。 应力的量和应力的极性（拉伸或压缩）可以通过应力膜的类型和厚度来控制。

公开(公告)号：US07494861B2

公开(公告)日：2009-02-24

申请号：US12013704

申请日：2008-01-14

Applicant: Jack Oon Chu ,  Bruce B. Doris ,  Meikei Ieong ,  Jing Wang

Inventor： Jack Oon Chu ,  Bruce B. Doris ,  Meikei Ieong ,  Jing Wang

IPC: H01L21/8238

CPC classification number: H01L29/7838 ,  H01L21/28017 ,  H01L29/105

Abstract: MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.

Abstract translation: 适用于栅极长度小于约40nm的MOSFET器件及其制造方法。 MOSFET器件包括由单晶Si基材料形成的接地平面。 Si基体层外延地设置在接地平面上。 体层掺杂了与地平面相反的杂质。 栅极具有中间功能函数的金属，其直接接触栅极绝缘体层。 栅极被图案化成小于约40nm，并且可能小于20nm的长度。 MOSFET的源极和漏极掺杂有与体层相同类型的掺杂剂。 在本发明的CMOS实施例中，NMOS和PMOS器件的栅极中的金属可以是相同的金属。

公开(公告)号：US20080261354A1

公开(公告)日：2008-10-23

申请号：US12145024

申请日：2008-06-24

Applicant: Meikei Ieong ,  Min Yang

Inventor： Meikei Ieong ,  Min Yang

IPC: H01L21/84

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  Y10S438/973

Abstract: The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present invention provides a method of integrating semiconductor devices such that pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane of a planar hybrid substrate. The method of the present invention also improves the performance of creating SOI-like devices with a combination of a buried insulator and counter-doping layers. The present invention also relates to semiconductor structures that are formed utilizing the method of the present invention.

Abstract translation: 本发明提供了一种集成半导体器件的方法，使得在混合基板的特定晶体取向上形成不同类型的器件，其增强了每种器件的性能。 具体地，本发明提供了一种集成半导体器件的方法，使得pFET位于（110）晶面上，而nFET位于平面混合衬底的（100）晶面上。 本发明的方法还通过埋层绝缘体和反掺杂层的组合来改进制造SOI类器件的性能。 本发明还涉及利用本发明的方法形成的半导体结构。

公开(公告)号：US20080254594A1

公开(公告)日：2008-10-16

申请号：US12143912

申请日：2008-06-23

Applicant: Kevin K. Chan ,  Meikei Ieong ,  Alexander Reznicek ,  Devendra K. Sadana ,  Leathen Shi ,  Min Yang

Inventor： Kevin K. Chan ,  Meikei Ieong ,  Alexander Reznicek ,  Devendra K. Sadana ,  Leathen Shi ,  Min Yang

IPC: H01L21/30

CPC classification number: H01L29/7842 ,  H01L21/2022 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78687

Abstract: Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

Abstract translation: 提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。 在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。 根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。 该方法提供混合基板，其中至少一个器件层包括应变Si。

公开(公告)号：US20080246090A1

公开(公告)日：2008-10-09

申请号：US12119765

申请日：2008-05-13

Applicant: Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  MeiKei Ieong ,  Erin Catherine Jones

Inventor： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  MeiKei Ieong ,  Erin Catherine Jones

IPC: H01L27/12

CPC classification number: H01L29/78648 ,  H01L21/0338 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42384

Abstract: A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

Abstract translation: 提供了具有横向排列的前（上）和后门的双栅极晶体管。 双栅晶体管包括在器件层下面的背栅热氧化层; 位于背栅极氧化物层下面的背栅电极; 位于器件层上方的前门热氧化物; 前栅极热氧化物上方的前栅极电极层，并与背栅电极垂直对准; 以及设置在背栅极热氧化物层上方的与第一栅极对称的晶体管体。 背栅电极具有形成在晶体管本体下方和在背栅电极的中心部分的任一侧上的氧化物层，从而将后栅极与前栅极自对准。 晶体管还包括在所述晶体管体的相对侧上的源极和漏极。