发明申请
- 专利标题： Methods and apparatuses for three dimensional integrated circuits
- 专利标题（中）： 三维集成电路的方法和装置
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申请号： US11821051申请日： 2007-06-20
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公开(公告)号： US20080315422A1公开(公告)日： 2008-12-25
- 发明人: John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
- 申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
- 主分类号： H01L21/4763
- IPC分类号： H01L21/4763 ; H01L21/44 ; H01L23/48
摘要：
Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit.
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