发明申请
US20090001479A1 TRANSISTOR HAVING REDUCED GATE RESISTANCE AND ENHANCED STRESS TRANSFER EFFICIENCY AND METHOD OF FORMING THE SAME 审中-公开
具有降低的栅极电阻和增强的应力传递效率的晶体管及其形成方法

  • 专利标题: TRANSISTOR HAVING REDUCED GATE RESISTANCE AND ENHANCED STRESS TRANSFER EFFICIENCY AND METHOD OF FORMING THE SAME
  • 专利标题(中): 具有降低的栅极电阻和增强的应力传递效率的晶体管及其形成方法
  • 申请号: US12026827
    申请日: 2008-02-06
  • 公开(公告)号: US20090001479A1
    公开(公告)日: 2009-01-01
  • 发明人: Maciej WiatrRoman BoschkePeter Javorka
  • 申请人: Maciej WiatrRoman BoschkePeter Javorka
  • 优先权: DE102007030054.0 20070629
  • 主分类号: H01L27/088
  • IPC分类号: H01L27/088 H01L21/8234
TRANSISTOR HAVING REDUCED GATE RESISTANCE AND ENHANCED STRESS TRANSFER EFFICIENCY AND METHOD OF FORMING THE SAME
摘要:
By removing an upper portion of a complex spacer structure, such as a triple spacer structure, an upper surface of an intermediate spacer element may be exposed, thereby enabling the removal of the outermost spacer and a material reduction of the intermediate spacer in a well-controllable common etch process. Consequently, sidewall portions of the gate electrode may be efficiently exposed for a subsequent silicidation process, while the residual reduced spacer provides sufficient process margins. Thereafter, highly stressed material may be deposited, thereby providing an enhanced stress transfer mechanism.
信息查询
0/0