公开(公告)号：US20110156172A1

公开(公告)日：2011-06-30

申请号：US12908053

申请日：2010-10-20

申请人： Stephan Kronholz ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

发明人： Stephan Kronholz ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66651

摘要： When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Moreover, the well dopant species is implanted after the recessing, thereby avoiding undue dopant loss. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.

摘要翻译： 当形成需要用于一种类型的晶体管的阈值调节半导体合金的复杂的栅电极结构时，在相应的有源区中形成凹部，从而在半导体材料的沉积期间提供优异的工艺均匀性。 此外，在凹陷之后注入阱掺杂剂物质，从而避免不必要的掺杂剂损失。 由于凹槽，可以在选择性外延生长工艺期间避免有源区的任何暴露的侧壁表面区域，从而显着地有助于提高包括高k金属栅叠层的晶体管的阈值稳定性。

公开(公告)号：US20110024846A1

公开(公告)日：2011-02-03

申请号：US12838810

申请日：2010-07-19

申请人： Thorsten Kammler ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

发明人： Thorsten Kammler ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823871 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104

摘要： In a static memory cell, the failure rate upon forming contact elements connecting an active region with a gate electrode structure formed above an isolation region may be significantly reduced by incorporating an implantation species at a tip portion of the active region through a sidewall of the isolation trench prior to filling the same with an insulating material. The implantation species may represent a P-type dopant species and/or an inert species for significantly modifying the material characteristics at the tip portion of the active region.

摘要翻译： 在静态存储单元中，通过在有源区的尖端部分通过隔离侧壁并入注入物质，可以显着地减少形成连接有源区与形成在隔离区上方的栅电极结构的接触元件之间的故障率 在用绝缘材料填充之前，该沟槽。 注入物质可以表示P型掺杂物种类和/或惰性物质，用于显着改变活性区的末端部分的材料特性。

公开(公告)号：US20090001479A1

公开(公告)日：2009-01-01

申请号：US12026827

申请日：2008-02-06

申请人： Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

发明人： Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/6659 ,  H01L21/28052 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/84 ,  H01L29/458 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/78621

摘要： By removing an upper portion of a complex spacer structure, such as a triple spacer structure, an upper surface of an intermediate spacer element may be exposed, thereby enabling the removal of the outermost spacer and a material reduction of the intermediate spacer in a well-controllable common etch process. Consequently, sidewall portions of the gate electrode may be efficiently exposed for a subsequent silicidation process, while the residual reduced spacer provides sufficient process margins. Thereafter, highly stressed material may be deposited, thereby providing an enhanced stress transfer mechanism.

摘要翻译： 通过去除诸如三重间隔物结构的复合间隔物结构的上部，中间间隔元件的上表面可能被暴露，从而能够去除最外侧间隔物并使中间间隔物的材料还原， 可控公共蚀刻工艺。 因此，栅电极的侧壁部分可以有效地暴露以用于随后的硅化工艺，而剩余的还原间隔物提供足够的工艺裕度。 此后，可以沉积高应力材料，从而提供增强的应力转移机制。

公开(公告)号：US08939765B2

公开(公告)日：2015-01-27

申请号：US12965118

申请日：2010-12-10

申请人： Stephan Kronholz ,  Peter Javorka ,  Maciej Wiatr ,  Roman Boschke ,  Christian Krueger

发明人： Stephan Kronholz ,  Peter Javorka ,  Maciej Wiatr ,  Roman Boschke ,  Christian Krueger

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7843 ,  H01L29/7848

摘要： In sophisticated semiconductor devices, the defect rate that may typically be associated with the provision of a silicon/germanium material in the active region of P-channel transistors may be significantly decreased by incorporating a carbon species prior to or during the selective epitaxial growth of the silicon/germanium material. In some embodiments, the carbon species may be incorporated during the selective growth process, while in other cases an ion implantation process may be used. In this case, superior strain conditions may also be obtained in N-channel transistors.

摘要翻译： 在复杂的半导体器件中，通常可以通过在P沟道晶体管的有源区中提供硅/锗材料相关联的缺陷率可以通过在选择性外延生长之前或期间引入碳物质而显着降低 硅/锗材料。 在一些实施方案中，可以在选择性生长过程中引入碳物质，而在其它情况下可以使用离子注入工艺。 在这种情况下，也可以在N沟道晶体管中获得优异的应变条件。

公开(公告)号：US08338892B2

公开(公告)日：2012-12-25

申请号：US12893808

申请日：2010-09-29

申请人： Stephan Kronholz ,  Roman Boschke ,  Maciej Wiatr ,  Peter Javorka

发明人： Stephan Kronholz ,  Roman Boschke ,  Maciej Wiatr ,  Peter Javorka

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/26586 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/82385 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845

摘要： In MOS transistor elements, a strain-inducing semiconductor alloy may be embedded in the active region with a reduced offset from the channel region by applying a spacer structure of reduced width. In order to reduce the probability of creating semiconductor residues at the top area of the gate electrode structure, a certain degree of corner rounding of the semiconductor material may be introduced, which may be accomplished by ion implantation prior to epitaxially growing the strain-inducing semiconductor material. This concept may be advantageously combined with the provision of sophisticated high-k metal gate electrodes that are provided in an early manufacturing stage.

摘要翻译： 在MOS晶体管元件中，通过施加减小的宽度的间隔结构，应变诱导半导体合金可以嵌入在有源区中，并且与沟道区的偏移减小。 为了降低在栅极电极结构的顶部区域产生半导体残留物的可能性，可以引入半导体材料的一定程度的角圆化，这可以在外延生长应变诱导半导体之前通过离子注入来实现 材料。 这个概念可以有利地结合提供在早期制造阶段中提供的复杂的高k金属栅电极。

公开(公告)号：US08481404B2

公开(公告)日：2013-07-09

申请号：US12838810

申请日：2010-07-19

申请人： Thorsten Kammler ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

发明人： Thorsten Kammler ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

IPC分类号： H01L21/76

CPC分类号： H01L21/823871 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104

摘要： In a static memory cell, the failure rate upon forming contact elements connecting an active region with a gate electrode structure formed above an isolation region may be significantly reduced by incorporating an implantation species at a tip portion of the active region through a sidewall of the isolation trench prior to filling the same with an insulating material. The implantation species may represent a P-type dopant species and/or an inert species for significantly modifying the material characteristics at the tip portion of the active region.

摘要翻译： 在静态存储单元中，通过在有源区的尖端部分通过隔离侧壁并入注入物质，可以显着地减少形成连接有源区与形成在隔离区上方的栅电极结构的接触元件之间的故障率 在用绝缘材料填充之前，该沟槽。 注入物质可以表示P型掺杂物种类和/或惰性物质，用于显着改变活性区的末端部分的材料特性。

公开(公告)号：US20110101469A1

公开(公告)日：2011-05-05

申请号：US12893808

申请日：2010-09-29

申请人： Stephan Kronholz ,  Roman Boschke ,  Maciej Wiatr ,  Peter Javorka

发明人： Stephan Kronholz ,  Roman Boschke ,  Maciej Wiatr ,  Peter Javorka

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/823842 ,  H01L21/26586 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/82385 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845

摘要： In MOS transistor elements, a strain-inducing semiconductor alloy may be embedded in the active region with a reduced offset from the channel region by applying a spacer structure of reduced width. In order to reduce the probability of creating semiconductor residues at the top area of the gate electrode structure, a certain degree of corner rounding of the semiconductor material may be introduced, which may be accomplished by ion implantation prior to epitaxially growing the strain-inducing semiconductor material. This concept may be advantageously combined with the provision of sophisticated high-k metal gate electrodes that are provided in an early manufacturing stage.

摘要翻译： 在MOS晶体管元件中，通过施加减小的宽度的间隔结构，应变诱导半导体合金可以嵌入在有源区中，并且与沟道区的偏移减小。 为了降低在栅极电极结构的顶部区域产生半导体残留物的可能性，可以引入半导体材料的一定程度的角圆化，这可以在外延生长应变诱导半导体之前通过离子注入来实现 材料。 这个概念可以有利地结合提供在早期制造阶段中提供的复杂的高k金属栅电极。

公开(公告)号：US08722486B2

公开(公告)日：2014-05-13

申请号：US12908053

申请日：2010-10-20

申请人： Stephan Kronholz ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

发明人： Stephan Kronholz ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66651

摘要： When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Moreover, the well dopant species is implanted after the recessing, thereby avoiding undue dopant loss. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.

摘要翻译： 当形成需要用于一种类型的晶体管的阈值调节半导体合金的复杂的栅电极结构时，在相应的有源区中形成凹部，从而在半导体材料的沉积期间提供优异的工艺均匀性。 此外，在凹陷之后注入阱掺杂剂物质，从而避免不必要的掺杂剂损失。 由于凹槽，可以在选择性外延生长工艺期间避免有源区的任何暴露的侧壁表面区域，从而显着地有助于提高包括高k金属栅叠层的晶体管的阈值稳定性。

公开(公告)号：US20110291163A1

公开(公告)日：2011-12-01

申请号：US12965118

申请日：2010-12-10

申请人： Stephan Kronholz ,  Peter Javorka ,  Maciej Wiatr ,  Roman Boschke ,  Christian Krueger

发明人： Stephan Kronholz ,  Peter Javorka ,  Maciej Wiatr ,  Roman Boschke ,  Christian Krueger

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7843 ,  H01L29/7848

摘要： In sophisticated semiconductor devices, the defect rate that may typically be associated with the provision of a silicon/germanium material in the active region of P-channel transistors may be significantly decreased by incorporating a carbon species prior to or during the selective epitaxial growth of the silicon/germanium material. In some embodiments, the carbon species may be incorporated during the selective growth process, while in other cases an ion implantation process may be used. In this case, superior strain conditions may also be obtained in N-channel transistors.

摘要翻译： 在复杂的半导体器件中，通常可以通过在P沟道晶体管的有源区中提供硅/锗材料相关联的缺陷率可以通过在选择性外延生长之前或期间引入碳物质而显着降低 硅/锗材料。 在一些实施方案中，可以在选择性生长过程中引入碳物质，而在其它情况下可以使用离子注入工艺。 在这种情况下，也可以在N沟道晶体管中获得优异的应变条件。

公开(公告)号：US08097519B2

公开(公告)日：2012-01-17

申请号：US12113271

申请日：2008-05-01

申请人： Maciej Wiatr ,  Markus Forsberg ,  Roman Boschke

发明人： Maciej Wiatr ,  Markus Forsberg ,  Roman Boschke

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/7843

摘要： By removing material during the formation of trench openings of isolation structures in an SOI device, the subsequent implantation process for defining the well region for a substrate diode may be performed on the basis of moderately low implantation energies, thereby increasing process uniformity and significantly reducing cycle time of the implantation process. Thus, enhanced reliability and stability of the substrate diode may be accomplished while also providing a high degree of compatibility with conventional manufacturing techniques.

摘要翻译： 通过在SOI器件中形成隔离结构的沟槽开口期间去除材料，用于限定衬底二极管的阱区的后续注入工艺可以在适度低的注入能量的基础上进行，从而增加工艺均匀性并显着减少循环 植入过程的时间。 因此，可以实现衬底二极管的增强的可靠性和稳定性，同时还提供与常规制造技术的高度兼容性。