An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second semiconductor layer provided on the first semiconductor layer to prevent diffusion of impurities from the first semiconductor layer to regions above the second semiconductor layer; and a third semiconductor layer provided on the second semiconductor layer, including a first source region having a second conductivity type, a first drain regions having the second conductivity type and a first channel region having the second conductivity type for each of the memory cell transistors.