发明申请
- 专利标题: Memory device, memory controller and memory system
- 专利标题(中): 内存设备,内存控制器和内存系统
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申请号: US12000953申请日: 2007-12-19
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公开(公告)号: US20090027988A1公开(公告)日: 2009-01-29
- 发明人: Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
- 申请人: Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
- 申请人地址: JP Aichi-Ken
- 专利权人: Toyoda Gosei Co., Ltd.
- 当前专利权人: Toyoda Gosei Co., Ltd.
- 当前专利权人地址: JP Aichi-Ken
- 优先权: JP2006-345415 20061222
- 主分类号: G11C7/00
- IPC分类号: G11C7/00 ; G11C8/00
摘要:
An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.
公开/授权文献
- US08015389B2 Memory device, memory controller and memory system 公开/授权日:2011-09-06