公开(公告)号：US20120327734A1

公开(公告)日：2012-12-27

申请号：US13485266

申请日：2012-05-31

申请人： Takahiko SATO

发明人： Takahiko SATO

IPC分类号： G11C5/14

CPC分类号： G11C11/4074 ,  G11C5/14 ,  G11C11/40615 ,  G11C11/4072

摘要： A memory has memory cells in a matrix; a first selection unit selecting any of first signal lines in the memory cells, in response to an access request; a second selection unit selecting any of second signal lines in the memory cells, after the first selection unit starts operating; a first voltage generation unit generating a first power supply voltage supplied to the first selection unit; a second voltage generation unit generating a second power supply voltage supplied to the second selection unit, when a start-up signal is active; a switch short-circuiting first and second power supply lines, when a short-circuit signal is active; and a power supply voltage control unit which activates the start-up signal in response to the access request, activates the short-circuit signal after a predetermined time elapses since activation of the start-up signal, deactivates the short-circuit signal and the start-up signal after completion of access operations.

摘要翻译： 存储器具有矩阵中的存储器单元; 第一选择单元，响应于访问请求，选择存储单元中的第一信号线中的任一个; 在第一选择单元开始操作之后，第二选择单元选择存储单元中的第二信号线中的任一个; 产生提供给第一选择单元的第一电源电压的第一电压产生单元; 第二电压产生单元，当启动信号有效时，产生提供给第二选择单元的第二电源电压; 当短路信号有效时，开关短路第一和第二电源线; 以及电源电压控制单元，其响应于所述访问请求而激活所述启动信号，在启动所述启动信号之后经过预定时间后激活所述短路信号，停用所述短路信号和所述启动 完成访问操作后的up信号。

公开(公告)号：US20090215378A1

公开(公告)日：2009-08-27

申请号：US12379502

申请日：2009-02-24

申请人： Nobuhiro Terai ,  Takahiko Sato ,  Shintaro Okawa ,  Katsuhiro Katagiri

发明人： Nobuhiro Terai ,  Takahiko Sato ,  Shintaro Okawa ,  Katsuhiro Katagiri

IPC分类号： B60H1/34

CPC分类号： B60H1/3428 ,  B60H2001/3478

摘要： An outer tube part 8 and an inner tube part 6 which is disposed in an interior of the outer tube part 8 are provided in an air-conditioning duct system which is connected to an air flow path downstream side of a vehicle air-conditioning system, and a side branch type silencer chamber 9 is defined by an inner circumferential surface of the outer tube part 8 and an outer circumferential surface of the inner tube part 6. In addition, an axis of at least a portion of the outer tube part 8 which confronts the inner tube part 6 and an axis of the inner tube part 6 are both made to be a straight line, and a register functioning part is provided in an interior of a portion of the outer tube part 8 which lies further downstream in an air flow path than the inner tube part 6.

摘要翻译： 设置在外管部8的内部的外管部8和内管部6设置在与车辆空调系统的空气流路下游侧连接的空调管道系统中， 侧管式消音器室9由外管部8的内周面和内管部6的外周面形成。此外，外管部8的至少一部分的轴线 内管部分6面对的内管部分6的轴线都被制成直线，并且在外管部分8的位于空气进一步下游的部分的内部设有对准功能部分 流路比内管部分6。

公开(公告)号：US07471585B2

公开(公告)日：2008-12-30

申请号：US11508917

申请日：2006-08-24

申请人： Naoharu Shinozaki ,  Tatsuya Kanda ,  Takahiko Sato ,  Akihiro Funyu

发明人： Naoharu Shinozaki ,  Tatsuya Kanda ,  Takahiko Sato ,  Akihiro Funyu

IPC分类号： G11C7/00

CPC分类号： G11C29/028 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C29/02 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/0403 ,  G11C2211/4061

摘要： A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.

摘要翻译： 响应于以预定周期产生的刷新请求输出刷新信号，并执行刷新操作。 刷新操作在访问请求与刷新请求之间发生冲突时结束。 因此，与访问请求相对应的访问操作可以随着访问时间的减少而更早地启动。 可以根据访问请求的提供时间改变刷新操作的结束时间，进一步减少访问时间。 由于形成用于将刷新操作的状态通知给外部的测试电路，因此可以在短时间内评估刷新操作的操作余量。 结果，可以减少半导体存储器的显影周期。

公开(公告)号：US20080304333A1

公开(公告)日：2008-12-11

申请号：US12136453

申请日：2008-06-10

申请人： Takahiko SATO

发明人： Takahiko SATO

IPC分类号： G11C7/00

CPC分类号： G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： A semiconductor integrated circuit includes a plurality of terminals, a first latch configured to, upon being uniquely specified by a first predetermined number of bits that are part of a plurality of bits entered through the terminals, store a second predetermined number of bits that are at least part of remaining bits left after excluding the first predetermined number of bits from the plurality of bits, and a second latch configured to, upon being uniquely specified by a third predetermined number of bits that are part of the plurality of bits entered through the terminals, store a fourth predetermined number of bits that are at least part of remaining bits left after excluding the third predetermined number of bits from the plurality of bits, wherein the first predetermined number is different from the third predetermined number, and the second predetermined number is different from the fourth predetermined number.

摘要翻译： 半导体集成电路包括多个终端，第一锁存器被配置为在由作为通过终端输入的多个比特的一部分的第一预定数量的比特唯一地指定时，存储第二预定数量的比特， 在从多个比特排除第一预定数量的比特之后剩下的剩余比特的剩余比特中的至少一部分，以及第二锁存器，被配置为在由作为通过终端输入的多个比特的一部分的第三预定数量的比特唯一地指定 存储从所述多个比特中排除所述第三预定比特数之后的剩余比特的剩余比特的至少一部分的第四预定数量的比特，其中，所述第一预定数不同于所述第三预定数，所述第二预定数是 与第四预定数量不同。

公开(公告)号：US20080146139A1

公开(公告)日：2008-06-19

申请号：US11987038

申请日：2007-11-27

申请人： Nobuhiro Terai ,  Minoru Shibata ,  Takahiko Sato

发明人： Nobuhiro Terai ,  Minoru Shibata ,  Takahiko Sato

IPC分类号： B60H1/34

CPC分类号： B60H1/3421 ,  B60H2001/3471

摘要： A low-profile air conditioning register is provided with a retainer, a bezel and a plurality of downstream fins. The bezel is arranged in such a manner as to position a lower long side of an opening of a passage portion in a downstream than an upper long side. The angle formed between a flange portion and the ventilation direction of the retainer is equal to or more than 60°. Further, the length of a corresponding line to a short side of the opening in a surface which is orthogonal to the ventilation direction is equal to or less than 35 mm. Further a lower inner wall in the passage portion is inclined with respect to the ventilation direction in such a manner as to become lower toward a downstream side. The lower inner wall surface has a length equal to or less than 10 mm along a thickness direction of the flange portion.

摘要翻译： 低调空调装置设置有保持器，挡板和多个下游翅片。 挡板布置成使得通道部分的开口的下长边位于比上长边的下游位置。 在凸缘部分和保持器的通气方向之间形成的角度等于或大于60°。 此外，与通气方向正交的表面中的开口的短边的对应线的长度等于或小于35mm。 此外，通道部分中的下部内壁相对于通气方向倾斜，朝向下游侧变低。 下部内壁面沿凸缘部的厚度方向的长度为10mm以下。

公开(公告)号：US07113441B2

公开(公告)日：2006-09-26

申请号：US11057841

申请日：2005-02-15

申请人： Naoharu Shinozaki ,  Tatsuya Kanda ,  Takahiko Sato ,  Akihiro Funyu

发明人： Naoharu Shinozaki ,  Tatsuya Kanda ,  Takahiko Sato ,  Akihiro Funyu

IPC分类号： G11C7/00

CPC分类号： G11C29/028 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C29/02 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/0403 ,  G11C2211/4061

摘要： A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.

摘要翻译： 响应于以预定周期产生的刷新请求输出刷新信号，并执行刷新操作。 刷新操作在访问请求与刷新请求之间发生冲突时结束。 因此，与访问请求相对应的访问操作可以随着访问时间的减少而更早地启动。 可以根据访问请求的提供时间改变刷新操作的结束时间，进一步减少访问时间。 由于形成用于将刷新操作的状态通知给外部的测试电路，因此可以在短时间内评估刷新操作的操作余量。 结果，可以减少半导体存储器的显影周期。

公开(公告)号：US20050116456A1

公开(公告)日：2005-06-02

申请号：US10988841

申请日：2004-11-16

申请人： Hiroyuki Tajima ,  Takahiko Sato ,  Osamu Fukawatase ,  Takeaki Kato

发明人： Hiroyuki Tajima ,  Takahiko Sato ,  Osamu Fukawatase ,  Takeaki Kato

IPC分类号： B60R21/00 ,  B60R21/02 ,  B60R21/04 ,  B60R21/045

CPC分类号： B60R21/045 ,  B60R2021/0051 ,  B60R2021/0414

摘要： The invention provides a vehicular shock absorbing body which absorbs a shock by a grid-like rib formed on a support plate portion and can inhibit a load point at an initial stage and a terminal stage, in a load-displacement (F-S) curve of the vehicular shock absorbing body. A shock absorbing body (40) used for absorbing a shock in a vehicle and made of a synthetic resin, is provided with a support plate portion (42), and a shock absorbing portion (45) formed in a grid shape on the support plate portion (42) by a plurality of thin ribs (44, 44), and plastically deforming at a time of applying a shock load so as to be absorbable a shock energy. A notch (a leading end side notch) 48 is formed between grid crossing points (46) in the thin rib (44) from a leading end side, and a notch (a root side notch) 50 is formed from a root side of the grid crossing points (46) so as to include the support plate portion (42), thereby inhibiting a load point from being generated at an initial stage and a terminal stage in the F-S curve.

摘要翻译： 本发明提供了一种车辆冲击吸收体，其通过形成在支撑板部分上的格栅状肋吸收冲击，并且能够抑制在初始阶段和末端阶段的载荷位置（FS）曲线中的载荷点 车辆减震体。 用于吸收车辆中的冲击并由合成树脂制成的减震体（40）设置有支撑板部分（42）和在支撑板上形成为格子状的冲击吸收部分（45） 部分（42）由多个薄肋（44,44）构成，并且在施加冲击载荷时塑性变形以便可吸收冲击能。 从前端侧在薄肋（44）的格栅交叉点（46）之间形成有切口（前端侧切口）48，并且从切口（根侧切口）50的根侧形成有切口 栅格交叉点（46），以包括支撑板部分（42），从而阻止在FS曲线的初始阶段和终端阶段产生负载点。

公开(公告)号：US20050099756A1

公开(公告)日：2005-05-12

申请号：US10833128

申请日：2004-04-28

申请人： Takahiko Sato

发明人： Takahiko Sato

IPC分类号： H01L21/822 ,  G11C7/00 ,  G11C7/10 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  H01L27/04

CPC分类号： G11C11/40603 ,  G11C7/1006 ,  G11C11/406 ,  G11C11/4076 ,  G11C2211/4061

摘要： A semiconductor device having a logic circuit, a delay circuit, and a processing circuit, wherein the logic circuit performs a logical operation process and outputs a first signal, the delay circuit delays an input signal and outputs a second signal, in parallel with the logical operation process of the logic circuit, and the processing circuit inputs the first signal and the second signal, and starts a process when both the first signal and the second signal are outputted.

摘要翻译： 一种具有逻辑电路，延迟电路和处理电路的半导体器件，其中所述逻辑电路执行逻辑运算处理并输出第一信号，所述延迟电路延迟输入信号并输出​​与所述逻辑电路并行的第二信号 并且处理电路输入第一信号和第二信号，并且当输出第一信号和第二信号两者时，开始处理。

公开(公告)号：US5571581A

公开(公告)日：1996-11-05

申请号：US338794

申请日：1994-11-08

申请人： Junji Koizumi ,  Hiroshi Mukai ,  Junji Takeuchi ,  Takahiko Sato

发明人： Junji Koizumi ,  Hiroshi Mukai ,  Junji Takeuchi ,  Takahiko Sato

IPC分类号： B29C45/16 ,  B32B25/08 ,  B60R13/04 ,  C08L23/08 ,  C08L23/10 ,  C08L23/16 ,  C08L51/06 ,  C08L53/00 ,  C08L53/02

CPC分类号： C08L23/10 ,  B29C45/1642 ,  B32B25/08 ,  B60R13/04 ,  C08L23/16 ,  C08L23/0815 ,  C08L23/0892 ,  C08L51/06 ,  C08L53/00 ,  C08L53/02

摘要： A long molded article having a skin layer composed of a thermoplastic elastomer, and a core layer coated with said skin layer which is composed of 30 to 70% by weight of a matrix phase composed of a polypropylene resin and 70 to 30% by weight of one dispersed phase selected from the group consisting of ethylene-.alpha.-olefin copolymers and styrene-based thermoplastic elastomers. According to the present invention, there can be obtained a long molded article such as a side molding for automobile, which is excellent in attractiveness after mounting, dimensional stability, etc.

摘要翻译： 具有由热塑性弹性体构成的表层的长成型品和涂有所述表皮层的芯层，其由30〜70重量％的由聚丙烯树脂构成的基质相和70〜30重量％ 一个分散相选​​自乙烯-α-烯烃共聚物和苯乙烯基热塑性弹性体。 根据本发明，可以获得诸如安装后的吸引力优异，尺寸稳定性等的用于汽车的侧面成型件的长模制品。

公开(公告)号：US08493400B2

公开(公告)日：2013-07-23

申请号：US12981075

申请日：2010-12-29

申请人： Takahiko Sato

发明人： Takahiko Sato

IPC分类号： G06F12/06 ,  G06F12/02

CPC分类号： G06F9/345 ,  G06T1/60 ,  G11C8/12 ,  H04N19/423 ,  H04N19/433

摘要： A memory device includes: a memory cell array which stores two-dimensionally arranged data in a plurality of memory unit regions selected by an address; an internal address control unit which generates an internal address which selects a memory unit region according to an external address; and a decoder which decodes the internal address and selects a memory unit region. The plurality of memory unit regions store data arranged in a first direction from among two-dimensionally arranged data according to a least-significant bit group of the internal address and store data arranged in a second direction from among the two-dimensionally arranged data according to a most-significant bit group of the address. The internal address control unit successively generates an internal address corresponding to the scan direction according to a scan direction control signal which controls a plurality of scan directions including at least an oblique direction of the two-dimensionally arranged data.

摘要翻译： 一种存储器件包括：存储单元阵列，其存储由地址选择的多个存储器单元区域中的二维布置数据; 内部地址控制单元，其生成根据外部地址选择存储单元区域的内部地址; 以及解码器，其对内部地址进行解码并选择存储器单元区域。 多个存储单元区域根据内部地址的最低有效位组存储从二维排列的数据中排列在第一方向上的数据，并且根据第二方向从第二方向存储布置在二维布置数据中的数据 一个最重要的位组的地址。 内部地址控制单元根据扫描方向控制信号连续地产生与扫描方向相对应的内部地址，该扫描方向控制信号控制至少包括二维布置数据的倾斜方向的扫描方向。