发明申请
US20090030660A1 METHOD AND APPARATUS FOR GENERATING FULLY DETAILED THREE-DIMENSIONAL ELECTRONIC PACKAGE AND PCB BOARD MODELS
审中-公开
用于产生完整的三维电子封装和PCB板模型的方法和装置
- 专利标题: METHOD AND APPARATUS FOR GENERATING FULLY DETAILED THREE-DIMENSIONAL ELECTRONIC PACKAGE AND PCB BOARD MODELS
- 专利标题(中): 用于产生完整的三维电子封装和PCB板模型的方法和装置
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申请号: US11782393申请日: 2007-07-24
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公开(公告)号: US20090030660A1公开(公告)日: 2009-01-29
- 发明人: Zeki Celik , Atila Mertol
- 申请人: Zeki Celik , Atila Mertol
- 申请人地址: US CA Milpitas
- 专利权人: LSI Logic Corporation
- 当前专利权人: LSI Logic Corporation
- 当前专利权人地址: US CA Milpitas
- 主分类号: G06F17/10
- IPC分类号: G06F17/10
摘要:
A process is provided, which includes receiving geometrical information for a plurality of layers of an electronic structure within at least one output data file from an electronic structure design tool. At least one numerical analysis data file is created from the output data file, which contains the geometrical information and has a file structure compatible with a numerical analysis tool for characterizing the electronic structure. The numerical analysis tool is used to read the numerical analysis data file and generate a three-dimensional meshed geometric model of the electronic structure from the numerical analysis data file, wherein the model includes three-dimensional geometric models of each layer. The model can then be used, for example, to solve numerical thermal, mechanical or electrical equations that are applied to the model.
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