发明申请
US20090034313A1 SEMICONDUCTOR MEMORY DEVICE AND LAYOUT STRUCTURE OF SUB-WORD LINE CONTROL SIGNAL GENERATOR 有权
子线控制信号发生器的半导体存储器件和布局结构

  • 专利标题: SEMICONDUCTOR MEMORY DEVICE AND LAYOUT STRUCTURE OF SUB-WORD LINE CONTROL SIGNAL GENERATOR
  • 专利标题(中): 子线控制信号发生器的半导体存储器件和布局结构
  • 申请号: US12177716
    申请日: 2008-07-22
  • 公开(公告)号: US20090034313A1
    公开(公告)日: 2009-02-05
  • 发明人: Dong-Su JANGIn-Chul JEONG
  • 申请人: Dong-Su JANGIn-Chul JEONG
  • 申请人地址: KR Gyeonggi-do
  • 专利权人: SAMSUNG ELECTRONICS CO., LTD.
  • 当前专利权人: SAMSUNG ELECTRONICS CO., LTD.
  • 当前专利权人地址: KR Gyeonggi-do
  • 优先权: KR2007-0077956 20070803
  • 主分类号: G11C5/02
  • IPC分类号: G11C5/02
SEMICONDUCTOR MEMORY DEVICE AND LAYOUT STRUCTURE OF SUB-WORD LINE CONTROL SIGNAL GENERATOR
摘要:
A semiconductor memory device and a layout structure of sub-word line control signal generators. The sub-word line control signal generators are configured to supply a sub-word line control signal of a predefined voltage level to a sub-word line driver to enable a sub-word line of a memory cell array. At least two sub-word line control signal generators are disposed, respectively, at edge areas of the memory cell array, to directly supply the sub-word line control signal to one selected sub-word line driver, thereby reducing the power consumption, including for example, VPP voltage. Embodiments of the present invention also reduce the number of VPP power lines, thereby lessening a noise disturbance.
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