公开(公告)号：US06665953B2

公开(公告)日：2003-12-23

申请号：US10108719

申请日：2002-03-29

申请人： Kyung Chul Woo ,  In Chul Jeong ,  Kyeong Hwan Kim ,  Choon Myun Chung ,  Mu Yong Choi

发明人： Kyung Chul Woo ,  In Chul Jeong ,  Kyeong Hwan Kim ,  Choon Myun Chung ,  Mu Yong Choi

IPC分类号： F26B508

CPC分类号： D06F25/00

摘要： Method for controlling a washing and drying machine, for improving drying performance, and saving energy, the method having a drying cycle for supplying heated air into an inner tub to dry laundry in the inner tub, wherein the drying cycle includes a plurality of drying steps each having the steps of rotating a pulsator for a preset time period, and rotating the inner tub for a preset time period in regular and reverse directions, for enhancing flow of the laundry.

摘要翻译： 用于控制洗涤和干燥机的方法，用于改善干燥性能和节约能量，所述方法具有用于将加热的空气供应到内桶中以干燥内桶中的衣物的干燥循环，其中干燥循环包括多个干燥步骤 每个都具有在预定时间段内旋转波轮的步骤，并且在正常和反向的方向上旋转内桶预设的时间段，以增加衣物的流动。

公开(公告)号：US08627174B2

公开(公告)日：2014-01-07

申请号：US12132754

申请日：2008-06-04

申请人： Kyung-hyun Kim ,  Kwang-il Park ,  In-chul Jeong

发明人： Kyung-hyun Kim ,  Kwang-il Park ,  In-chul Jeong

IPC分类号： G11C29/00

CPC分类号： H04L1/0042

摘要： In one aspect, a memory device includes a memory cell array, parallel internal data paths which transmit internal data to and from the memory cell array, a data driver which transmits and receives external data, and a data buffer which delays and transfers the external data received by the data driver to the internal data paths, and which delays and transfers the internal data transmitted from the memory cell array to the data driver. The memory device further includes an error correction code generator which generates an error correction code (EC) based on the internal data transmitted on the internal data paths, an EC buffer which delays the error correction code generated by the error correction code generator, an EC driver which transmits the error correction codes delayed by the EC buffer, and a latency controller which variably controls a delay time of at least one of the data buffer and the EC buffer.

摘要翻译： 一方面，存储器件包括存储单元阵列，将内部数据传送到存储单元阵列和从存储单元阵列发送内部数据的并行内部数据路径，发送和接收外部数据的数据驱动器以及延迟和传送外部数据的数据缓冲器 由数据驱动器接收到内部数据路径，并且延迟并将从存储单元阵列发送的内部数据传送到数据驱动器。 存储装置还包括纠错码发生器，该纠错码产生器基于在内部数据路径上发送的内部数据产生纠错码（EC），延迟由纠错码发生器产生的纠错码的EC缓冲器，EC 发送由EC缓冲器延迟的纠错码的驱动器，以及可变地控制数据缓冲器和EC缓冲器中的至少一个的延迟时间的等待时间控制器。

公开(公告)号：US08125249B2

公开(公告)日：2012-02-28

申请号：US12661668

申请日：2010-03-22

申请人： In-Chul Jeong

发明人： In-Chul Jeong

IPC分类号： G01R23/02 ,  G01R23/12

CPC分类号： H03K5/133 ,  G11C19/00 ,  G11C19/28 ,  H03L7/0812

摘要： A frequency measuring circuit and a semiconductor device having the frequency measuring circuit include a divided and shifted clock signal generator, a delayed clock signal generator and a phase detecting unit. The divided and shifted clock signal generator divides a frequency of a clock signal input from an exterior to output a frequency-divided clock signal, and delays the frequency-divided clock signal by a time proportional to a period of the clock signal to output a shifted clock signal. The delayed clock signal generator delays the frequency-divided clock signal by a fixed time to generate a plurality of delayed clock signals. The phase detecting unit receives the plurality of delayed clock signals and the shifted clock signal and detects a phase difference between each of the plurality of delayed clock signals and the shifted clock signal to output a plurality of phase detecting signals that represent information related to a frequency of the clock signal.

摘要翻译： 具有频率测量电路的频率测量电路和半导体器件包括分频移位时钟信号发生器，延迟时钟信号发生器和相位检测单元。 分频移位时钟信号发生器分频从外部输入的时钟信号的频率，以输出分频时钟信号，并将分频时钟信号延迟与时钟信号周期成比例的时间，以输出偏移 时钟信号。 延迟时钟信号发生器将分频时钟信号延迟固定时间以产生多个延迟的时钟信号。 相位检测单元接收多个延迟的时钟信号和移位的时钟信号，并且检测多个延迟时钟信号中的每一个与移位的时钟信号之间的相位差，以输出表示与频率有关的信息的多个相位检测信号 的时钟信号。

公开(公告)号：US07869241B2

公开(公告)日：2011-01-11

申请号：US12220422

申请日：2008-07-24

申请人： Je-Min Yu ,  In-Chul Jeong

发明人： Je-Min Yu ,  In-Chul Jeong

IPC分类号： G11C5/02

CPC分类号： G11C11/4085 ,  G11C8/08 ,  G11C8/14

摘要： A memory core capable of decreasing the area of core conjunction region is disclosed. The memory core includes a first sub word-line driving circuit and a first sub word-line control signal generating circuit. The first sub word-line driving circuit is disposed in a first region, and generates a first word-line driving signal to provide the first word-line driving signal to an array unit. The first sub word-line control signal generating circuit is disposed in the first region, and generates the first sub word-line control signal based on a sub word-line driving signal. Therefore, the memory core has a small size and, consequently so can the semiconductor device.

公开(公告)号：US07359280B2

公开(公告)日：2008-04-15

申请号：US11336831

申请日：2006-01-23

申请人： Soo-Bong Chang ,  In-Chul Jeong ,  Jun-Hyung Kim ,  Seung-Min Oh ,  Jung-Hwa Lee

发明人： Soo-Bong Chang ,  In-Chul Jeong ,  Jun-Hyung Kim ,  Seung-Min Oh ,  Jung-Hwa Lee

IPC分类号： G11C8/00

CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/11898

摘要： A layout structure for sub word line drivers and method thereof. The example layout structure may include at least one N-channel transistor arrangement having a cross sectional width and a cross sectional length, the N-channel transistor arrangement oriented such that the cross sectional length extends along a first direction, the first direction oriented along a sub word line driver from a first sub array block to a second sub array block. The example method may arrange the at least one N-channel transistor between the first and second sub array blocks.

摘要翻译： 子字线驱动器的布局结构及其方法。 示例性布局结构可以包括具有横截面宽度和横截面长度的至少一个N沟道晶体管布置，N沟道晶体管布置方向使得横截面长度沿着第一方向延伸，第一方向沿着第一方向 子字线驱动器从第一子阵列块到第二子阵列块。 该示例性方法可以在第一和第二子阵列块之间布置至少一个N沟道晶体管。

公开(公告)号：US20080056033A1

公开(公告)日：2008-03-06

申请号：US11895250

申请日：2007-08-23

申请人： In-Chul Jeong

发明人： In-Chul Jeong

IPC分类号： G11C8/00 ,  G11C17/18 ,  G11C29/00

CPC分类号： G11C8/18 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4087 ,  G11C29/842 ,  G11C2207/2272

摘要： A semiconductor memory device includes a delay time selecting portion for outputting, as a final read/write command, an internal read/write command that corresponds to an external read/write command and is synchronized with an external clock rising edge at a tRCD time without any delay when an address is applied before an address setup time based on the external clock rising edge of a previously set tRCD time, a decoder for decoding an address applied from an external portion with the read/write command to output a decoded address, and a selecting portion for receiving the decoded address to select a memory cell of a memory cell array in response to the final read/write command.

摘要翻译： 半导体存储器件包括延迟时间选择部分，用于作为最终读/写命令输出与外部读/写命令相对应的内部读/写命令，并且在tRCD时间与外部时钟上升沿同步而没有 基于先前设置的tRCD时间的外部时钟上升沿地址建立时间之前应用地址的任何延迟，用于对从外部施加的地址进行解码以用于输出解码的地址的解码器，以及 选择部分，用于接收解码的地址以响应于最终的读/写命令来选择存储单元阵列的存储单元。

公开(公告)号：US20070151282A1

公开(公告)日：2007-07-05

申请号：US11611340

申请日：2006-12-15

申请人： Kyung Han Jeong ,  In Chul Jeong ,  Nam Gi Lee

发明人： Kyung Han Jeong ,  In Chul Jeong ,  Nam Gi Lee

IPC分类号： F25C5/08 ,  F25C1/00

CPC分类号： F25C1/04 ,  F25C5/08 ,  F25C2305/022 ,  F25C2400/06 ,  F25C2600/04

摘要： An icemaker and a method for controlling the same are disclosed. An object of the present invention is to provide an icemaker and a method for controlling the same, which has an improved structure to make a lot of ice in a short time. an icemaker includes an ice tray rotatable with at least one column of ice making chambers formed therein to make ice; an ejector rotatably provided in each ice making chamber to eject the ice formed in the ice making chamber; an operation device which rotates the ice tray; and a separation device which separates the ice from the ice tray. The separation device may be a heater which heats the ice. Preferably, the heater is operated until adhesive force which acts between the ice and the ice tray is smaller than pushing force in which the ejector pushes the ice.

摘要翻译： 公开了一种制冰机及其控制方法。 本发明的目的是提供一种制冰机及其控制方法，其具有改进的结构，以在短时间内制造大量的冰。 一个制冰机包括一个可与其中形成的至少一列制冰室一起旋转以制冰的冰盘; 一个可旋转地设置在每个制冰室中以喷射在制冰室中形成的冰的喷射器; 使冰盘旋转的操作装置; 以及将冰与冰盘分开的分离装置。 分离装置可以是加热器的加热器。 优选地，加热器被操作直到作用在冰和冰盘之间的粘合力小于喷射器推动冰的推动力。

公开(公告)号：US20060125523A1

公开(公告)日：2006-06-15

申请号：US11298201

申请日：2005-12-08

申请人： In-Chul Jeong

发明人： In-Chul Jeong

IPC分类号： H03K19/0175

CPC分类号： H03K5/082 ,  H03K5/003

摘要： We describe an input circuit and method. The input circuit includes a variable reference level generator that increases a level of a reference signal in proportion to a time when an input signal transits from a low level to a high level and decreases the level of the reference signal in proportion to a time when the input signal transits from a high level to a low level. An analyzer compares the level of the input signal with the level of the reference signal, determines the level of the input signal, and outputs a signal based on the comparison. The input circuit and method widen the minimum difference between the input and reference signal to facilitate analysis of the input signal.

摘要翻译： 我们描述一种输入电路和方法。 输入电路包括可变参考电平发生器，其与输入信号从低电平转换到高电平的时间成比例地增加参考信号的电平，并且与参考信号的电平成比例地降低参考信号的电平 输入信号从高电平转换到低电平。 分析仪将输入信号的电平与参考信号的电平进行比较，确定输入信号的电平，并根据比较输出信号。 输入电路和方法扩大了输入和参考信号之间的最小差异，便于分析输入信号。

公开(公告)号：US20140016420A1

公开(公告)日：2014-01-16

申请号：US13899949

申请日：2013-05-22

申请人： In-chul JEONG

发明人： In-chul JEONG

IPC分类号： G11C7/06

CPC分类号： G11C7/06 ,  G11C5/025 ,  G11C7/18

摘要： A semiconductor memory device includes a sense amplifier circuit region including first wells disposed in a first direction, a driving circuit region including second wells disposed in a second direction, and a conjunction region disposed at an intersection region of the sense amplifier circuit region and the driving circuit region, a part of each of the first wells extending from the sense amplifier circuit region into the conjunction region, and the second wells being outside of the conjunction region.

摘要翻译： 一种半导体存储器件，包括读出放大器电路区域，包括沿第一方向布置的第一阱，包括沿第二方向布置的第二阱的驱动电路区域和布置在读出放大器电路区域与驱动 电路区域，每个第一阱的一部分从读出放大器电路区域延伸到连接区域中，第二阱在结合区域之外。

公开(公告)号：US20130308405A1

公开(公告)日：2013-11-21

申请号：US13896511

申请日：2013-05-17

申请人： In-Chul JEONG

发明人： In-Chul JEONG

IPC分类号： G11C7/00

CPC分类号： G11C11/40626 ,  G11C7/00 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4087

摘要： A semiconductor memory device includes a memory cell array, a refresh control circuit, an address counter and an address converter. The memory cell array includes a plurality of memory cells. The refresh control circuit is configured to receive a refresh command and output m refresh control signals during one refresh cycle for refreshing all the memory cells of the semiconductor memory device. The address counter is configured to generate counting signals for refreshing memory cells in response to the m refresh control signals. The address converter is configured to receive the counting signals and output refresh addresses by converting the counting signals in response to a cycle select signal. The address converter is configured to output refresh addresses such that the number of m refresh control signals during one refresh cycle is variable.