发明申请
- 专利标题： DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR
- 专利标题（中）： 双端口增益单元与侧面和顶部读取晶体管
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申请号： US12254960申请日： 2008-10-21
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公开(公告)号： US20090047756A1公开(公告)日： 2009-02-19
- 发明人: Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
- 申请人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
- 申请人地址： US NY Armonk
- 专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址： US NY Armonk
- 主分类号： H01L21/84
- IPC分类号： H01L21/84 ; H01L21/8242
摘要：
A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
公开/授权文献
- US07790530B2 Dual port gain cell with side and top gated read transistor 公开/授权日：2010-09-07
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