A non-volatile memory having a gate structure and a source/drain region is provided. The gate structure is disposed on a substrate. The gate structure includes a pair of floating gates, tunneling dielectric layers, a control gate and an inter-gate dielectric layer. The floating gates are disposed on the substrate. Each tunneling dielectric layer is disposed between each floating gate and the substrate. The control gate is disposed on the substrate between the pair of the floating gates and covers a top surface and sidewalls of each floating gate. The inter-gate dielectric layer is disposed between the control gate and each of the floating gates, disposed between the control gate and each of the tunneling dielectric layers, and disposed between the control gate and the substrate. The source/drain region is disposed in the substrate at respective sides of the gate structure.