发明申请
US20090049287A1 Stall-Free Pipelined Cache for Statically Scheduled and Dispatched Execution
有权
用于静态计划和分派执行的无失调流水线缓存
- 专利标题: Stall-Free Pipelined Cache for Statically Scheduled and Dispatched Execution
- 专利标题(中): 用于静态计划和分派执行的无失调流水线缓存
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申请号: US11839856申请日: 2007-08-16
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公开(公告)号: US20090049287A1公开(公告)日: 2009-02-19
- 发明人: Chris Yoochang Chung
- 申请人: Chris Yoochang Chung
- 主分类号: G06F9/318
- IPC分类号: G06F9/318
摘要:
This invention provides flexible load latency to pipeline cache misses. A memory controller selects the output of one of a set of cascades inserted execute stages. This selection may be controlled by a latency field in a load instruction or by a latency specification of a prior instruction. This invention is useful in the great majority of cases where the code can tolerate incremental increases in load latency for a reduction in cache miss penalty.