发明申请
- 专利标题: METHOD AND APPARATUS FOR CLOCK CYCLE STEALING
- 专利标题(中): 用于时钟循环的方法和装置
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申请号: US11841179申请日: 2007-08-31
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公开(公告)号: US20090063888A1公开(公告)日: 2009-03-05
- 发明人: Spencer M. Gold , Bill K.C. Kwan , Craig D. Eaton
- 申请人: Spencer M. Gold , Bill K.C. Kwan , Craig D. Eaton
- 主分类号: G06F1/06
- IPC分类号: G06F1/06
摘要:
A method for producing a plurality of clock signals. The method includes generating a reference clock signal using a phase locked loop (PLL). The reference clock signal is then provided to each of a plurality of clock divider units which each divide the received reference clock signal to produce a corresponding divided clock signal. The method then removes one or more clock cycles (per a given number of cycles) in order to produce a plurality of domain clock signals each having an effective frequency based on a frequency and a number of cycles removed from the correspondingly received divided clock signal.
公开/授权文献
- US07913103B2 Method and apparatus for clock cycle stealing 公开/授权日:2011-03-22