Provided are an embedded semiconductor device and a method of manufacturing an embedded semiconductor device. In a method of manufacturing the embedded semiconductor device, layers of at least one cell gate stack may be formed in a cell area of a substrate. A logic gate structure may be formed in a logic area of the substrate. First source/drain regions may be formed adjacent to the logic gate structure, and metal silicide patterns may be formed on the logic gate structure and the first source/drain regions. At least one hard mask may be formed on the layers of the at least one cell gate stack, and a blocking pattern may be formed to cover the logic gate structure and the first source/drain regions. The at least one cell gate stack may be formed in the cell area by etching the layers of the at least one cell gate stack using the at least one hard mask as an etching mask. A memory transistor in the cell area may have an increased integration degree and a logic transistor in the logic area may have an increased response speed and a decreased resistance.