公开(公告)号：US20100285641A1

公开(公告)日：2010-11-11

申请号：US12836066

申请日：2010-07-14

申请人： Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Young-Ho Kim ,  Myung-Jo Chun ,  Jung-Ho Moon

发明人： Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Young-Ho Kim ,  Myung-Jo Chun ,  Jung-Ho Moon

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L27/105 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/1052 ,  H01L27/11266 ,  H01L27/11293

摘要： A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off-cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity.

摘要翻译： 可以稳定地输出数据的掩模只读存储器（ROM）装置包括接通电池和截止电池。 开放单元包括衬底上的孔上栅极结构和衬底内的电池单元结结构。 离子电池包括在衬底上的离子电池栅极结构和衬底内的细胞外结合结构。 单体栅极结构包括单元间栅极绝缘膜，单晶体栅极电极和单元间栅极间隔物。 该单电池结结构包括具有第一极性的第一和第二开孔离子注入区和第二极性的第三和第四接通电离子注入区。 离群栅极结构包括离子栅极绝缘膜，离子阱栅极电极和非电池栅极间隔物。 离电池结结构包括具有第一极性的第一和第二离子外离子注入区域和第二极性的第三离子间离子注入区域。

公开(公告)号：US20100059888A1

公开(公告)日：2010-03-11

申请号：US12590482

申请日：2009-11-09

申请人： Yong-Kyu Lee ,  Hee-Seog JEON ,  Jeong-Uk HAN ,  Young-Ho Kim ,  Myung-Jo Chun

发明人： Yong-Kyu Lee ,  Hee-Seog JEON ,  Jeong-Uk HAN ,  Young-Ho Kim ,  Myung-Jo Chun

IPC分类号： H01L23/532 ,  H01L23/48

CPC分类号： H01L27/1021

摘要： A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.

摘要翻译： 掩模只读存储器（ROM）包括形成在基板上的电介质层和形成在电介质层上的多个第一导电线。 在第一导线中形成多个二极管，并且为第一组二极管形成多个最终通孔，每个二极管表示第一类型的存储单元，没有形成用于第二组二极管的最终通孔，每个二极管表示 第二种类型的存储单元。 多个第二导电线中的每一个形成在二极管的列上。

公开(公告)号：US20080080244A1

公开(公告)日：2008-04-03

申请号：US11818238

申请日：2007-06-13

申请人： Yong-Kyu Lee ,  Myung-Jo Chun ,  Young-Ho Kim ,  Hee-Seog Jeon ,  Jeong-Uk Han

发明人： Yong-Kyu Lee ,  Myung-Jo Chun ,  Young-Ho Kim ,  Hee-Seog Jeon ,  Jeong-Uk Han

IPC分类号： G11C11/34 ,  G11C7/00

CPC分类号： G11C16/0433 ,  G11C8/10 ,  G11C16/08 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534

摘要： A non-volatile integrated circuit memory device may include a semiconductor substrate having first and second electrically isolated wells of a same conductivity type. A first plurality of non-volatile memory cell transistors may be provided on the first well, and a second plurality of non-volatile memory cell transistors may be provided on the second well. A local control gate line may be electrically coupled with the first and second pluralities of non-volatile memory cell transistors, and a group selection transistor may be electrically coupled between the local control gate line and a global control gate line. More particularly, the group selection transistor may be configured to electrically couple and decouple the local control gate line and the global control gate line responsive to a group selection gate signal applied to a gate of the group selection transistor. Related methods and systems are also discussed.

摘要翻译： 非易失性集成电路存储器件可以包括具有相同导电类型的第一和第二电隔离阱的半导体衬底。 可以在第一阱上提供第一多个非易失性存储单元晶体管，并且可以在第二阱上提供第二多个非易失性存储单元晶体管。 本地控制栅极线可以与第一和第二多个非易失性存储单元晶体管电耦合，并且组选择晶体管可以电耦合在本地控制栅极线和全局控制栅极线之间。 更具体地，组选择晶体管可以被配置为响应于施加到组选择晶体管的栅极的组选择栅极信号来电耦合和去耦合本地控制栅极线和全局控制栅极线。 还讨论了相关方法和系统。

公开(公告)号：US07638387B2

公开(公告)日：2009-12-29

申请号：US11823381

申请日：2007-06-27

申请人： Yong-Kyu Lee ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Young-Ho Kim ,  Myung-Jo Chun

发明人： Yong-Kyu Lee ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Young-Ho Kim ,  Myung-Jo Chun

IPC分类号： H01L21/8234

CPC分类号： H01L27/1021

摘要： A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.

摘要翻译： 掩模只读存储器（ROM）包括形成在基板上的电介质层和形成在电介质层上的多个第一导电线。 在第一导线中形成多个二极管，并且为第一组二极管形成多个最终通孔，每个二极管表示第一类型的存储单元，没有形成用于第二组二极管的最终通孔，每个二极管表示 第二种类型的存储单元。 多个第二导电线中的每一个形成在二极管的列上。

公开(公告)号：US08053342B2

公开(公告)日：2011-11-08

申请号：US12836066

申请日：2010-07-14

申请人： Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Young-Ho Kim ,  Myung-Jo Chun ,  Jung-Ho Moon

发明人： Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Young-Ho Kim ,  Myung-Jo Chun ,  Jung-Ho Moon

IPC分类号： H01L21/8238

CPC分类号： H01L27/105 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/1052 ,  H01L27/11266 ,  H01L27/11293

摘要： A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off-cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity.

摘要翻译： 可以稳定地输出数据的掩模只读存储器（ROM）装置包括接通电池和截止电池。 开放单元包括衬底上的孔上栅极结构和衬底内的电池单元结结构。 离子电池包括在衬底上的离子电池栅极结构和衬底内的细胞外结合结构。 单体栅极结构包括单元间栅极绝缘膜，单晶体栅极电极和单元间栅极间隔物。 该单电池结结构包括具有第一极性的第一和第二开孔离子注入区和第二极性的第三和第四接通电离子注入区。 离群栅极结构包括离子栅极绝缘膜，离子阱栅极电极和非电池栅极间隔物。 离电池结结构包括具有第一极性的第一和第二离子外离子注入区域和第二极性的第三离子间离子注入区域。

公开(公告)号：US20090065845A1

公开(公告)日：2009-03-12

申请号：US12230938

申请日：2008-09-08

申请人： Young-Ho Kim ,  Hee-Seog Jeon ,  Yong-Kyu Lee

发明人： Young-Ho Kim ,  Hee-Seog Jeon ,  Yong-Kyu Lee

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11529 ,  H01L29/665 ,  H01L29/7833

摘要： Provided are an embedded semiconductor device and a method of manufacturing an embedded semiconductor device. In a method of manufacturing the embedded semiconductor device, layers of at least one cell gate stack may be formed in a cell area of a substrate. A logic gate structure may be formed in a logic area of the substrate. First source/drain regions may be formed adjacent to the logic gate structure, and metal silicide patterns may be formed on the logic gate structure and the first source/drain regions. At least one hard mask may be formed on the layers of the at least one cell gate stack, and a blocking pattern may be formed to cover the logic gate structure and the first source/drain regions. The at least one cell gate stack may be formed in the cell area by etching the layers of the at least one cell gate stack using the at least one hard mask as an etching mask. A memory transistor in the cell area may have an increased integration degree and a logic transistor in the logic area may have an increased response speed and a decreased resistance.

摘要翻译： 提供了嵌入式半导体器件和制造嵌入式半导体器件的方法。 在制造嵌入式半导体器件的方法中，可以在衬底的单元区域中形成至少一个单元栅极堆叠的层。 逻辑门结构可以形成在衬底的逻辑区域中。 可以在逻辑门结构附近形成第一源极/漏极区，并且可以在逻辑门结构和第一源极/漏极区上形成金属硅化物图案。 可以在至少一个单元栅极堆叠的层上形成至少一个硬掩模，并且可以形成阻挡图案以覆盖逻辑门结构和第一源极/漏极区域。 可以通过使用至少一个硬掩模作为蚀刻掩模来蚀刻至少一个单元栅极堆叠的层而在单元区域中形成至少一个单元栅极堆叠。 单元区域中的存储晶体管可以具有增加的积分度，并且逻辑区域中的逻辑晶体管可以具有增加的响应速度和降低的电阻。

公开(公告)号：US20080179692A1

公开(公告)日：2008-07-31

申请号：US12013618

申请日：2008-01-14

申请人： Myung-Jo Chun ,  Hee-Seog Jeon ,  Yong-Kyu Lee ,  Young-Ho Kim

发明人： Myung-Jo Chun ,  Hee-Seog Jeon ,  Yong-Kyu Lee ,  Young-Ho Kim

IPC分类号： H01L27/112 ,  H01L21/8234

CPC分类号： H01L27/11293 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11266 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/665

摘要： A mask read only memory (MROM) device includes first and second gate electrodes formed at on-cell and off-cell regions of a substrate, respectively. A first impurity region is formed at the on-cell region of the substrate so as to be adjacent the first gate electrode. A second impurity region including the same conductivity type as that of the first impurity region is formed at the off-cell region of the substrate so as to be spaced apart from a sidewall of the second gate electrode. A fourth impurity region is formed at the off-cell region to extend from the second impurity region and to overlap with the sidewall of the second gate electrode. The fourth impurity region has a conductivity type opposite to that of the second impurity region and a depth greater than that of the second impurity region.

摘要翻译： 掩模只读存储器（MROM）器件分别包括形成在衬底的单元和离子区域的第一和第二栅电极。 第一杂质区形成在基板的单电池区域上，以便与第一栅电极相邻。 形成与第一杂质区相同导电类型的第二杂质区，以与第二栅电极的侧壁间隔开。 第四杂质区形成在离电池区域，从第二杂质区延伸并与第二栅电极的侧壁重叠。 第四杂质区域具有与第二杂质区域相反的导电类型，并且深度大于第二杂质区域的深度。

公开(公告)号：US20080003810A1

公开(公告)日：2008-01-03

申请号：US11823381

申请日：2007-06-27

申请人： Yong-Kyu Lee ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Young-Ho Kim ,  Myung-Jo Chun

发明人： Yong-Kyu Lee ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Young-Ho Kim ,  Myung-Jo Chun

IPC分类号： H01L21/4763

CPC分类号： H01L27/1021

摘要： A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.

摘要翻译： 掩模只读存储器（ROM）包括形成在基板上的电介质层和形成在电介质层上的多个第一导电线。 在第一导线中形成多个二极管，并且为第一组二极管形成多个最终通孔，每个二极管表示第一类型的存储单元，没有形成用于第二组二极管的最终通孔，每个二极管表示 第二种类型的存储单元。 多个第二导电线中的每一个形成在二极管的列上。

公开(公告)号：US07777256B2

公开(公告)日：2010-08-17

申请号：US12132148

申请日：2008-06-03

申请人： Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Young-Ho Kim ,  Myung-Jo Chun ,  Jung-Ho Moon

发明人： Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Young-Ho Kim ,  Myung-Jo Chun ,  Jung-Ho Moon

IPC分类号： H01L21/8238

CPC分类号： H01L27/105 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/1052 ,  H01L27/11266 ,  H01L27/11293

摘要： A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off -cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity.

摘要翻译： 可以稳定地输出数据的掩模只读存储器（ROM）装置包括接通电池和截止电池。 开放单元包括衬底上的孔上栅极结构和衬底内的电池单元结结构。 离子电池包括在衬底上的离子栅极结构和衬底内的离子阱结结构。 单体栅极结构包括单元间栅极绝缘膜，单晶体栅极电极和单元间栅极间隔物。 该单电池结结构包括具有第一极性的第一和第二开孔离子注入区和第二极性的第三和第四接通电离子注入区。 离群栅极结构包括离子栅极绝缘膜，离子阱栅极电极和非电池栅极间隔物。 离电池结结构包括具有第一极性的第一和第二离子外离子注入区域和第二极性的第三离子间离子注入区域。

公开(公告)号：US07733696B2

公开(公告)日：2010-06-08

申请号：US11818238

申请日：2007-06-13

申请人： Yong-Kyu Lee ,  Myung-Jo Chun ,  Young-Ho Kim ,  Hee-Seog Jeon ,  Jeong-Uk Han

发明人： Yong-Kyu Lee ,  Myung-Jo Chun ,  Young-Ho Kim ,  Hee-Seog Jeon ,  Jeong-Uk Han

IPC分类号： G11C11/34

CPC分类号： G11C16/0433 ,  G11C8/10 ,  G11C16/08 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534

摘要： A non-volatile integrated circuit memory device may include a semiconductor substrate having first and second electrically isolated wells of a same conductivity type. A first plurality of non-volatile memory cell transistors may be provided on the first well, and a second plurality of non-volatile memory cell transistors may be provided on the second well. A local control gate line may be electrically coupled with the first and second pluralities of non-volatile memory cell transistors, and a group selection transistor may be electrically coupled between the local control gate line and a global control gate line. More particularly, the group selection transistor may be configured to electrically couple and decouple the local control gate line and the global control gate line responsive to a group selection gate signal applied to a gate of the group selection transistor. Related methods and systems are also discussed.

摘要翻译： 非易失性集成电路存储器件可以包括具有相同导电类型的第一和第二电隔离阱的半导体衬底。 可以在第一阱上提供第一多个非易失性存储单元晶体管，并且可以在第二阱上提供第二多个非易失性存储单元晶体管。 本地控制栅极线可以与第一和第二多个非易失性存储单元晶体管电耦合，并且组选择晶体管可以电耦合在本地控制栅极线和全局控制栅极线之间。 更具体地，组选择晶体管可以被配置为响应于施加到组选择晶体管的栅极的组选择栅极信号来电耦合和去耦合本地控制栅极线和全局控制栅极线。 还讨论了相关方法和系统。