发明申请
- 专利标题： Metal High-K Transistor Having Silicon Sidewall for Reduced Parasitic Capacitance, and Process to Fabricate Same
- 专利标题（中）： 具有减少寄生电容的硅侧壁的金属高K晶体管及其制造方法
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申请号： US11852359申请日： 2007-09-10
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公开(公告)号： US20090065876A1公开(公告)日： 2009-03-12
- 发明人: Leland Chang , Isaac Lauer , Renee T. Mo , Jeffrey W. Sleight
- 申请人： Leland Chang , Isaac Lauer , Renee T. Mo , Jeffrey W. Sleight
- 主分类号： H01L29/78
- IPC分类号： H01L29/78 ; H01L21/3205
摘要：
A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.
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