发明申请
US20090065955A1 METHOD AND STRUCTURES FOR ACCELERATED SOFT-ERROR TESTING 有权
用于加速软错误测试的方法和结构

METHOD AND STRUCTURES FOR ACCELERATED SOFT-ERROR TESTING
摘要:
An integrated circuit, method of forming the integrated circuit and a method of testing the integrated circuit for soft-error fails. The integrated circuit includes: a silicon substrate; a dielectric layer formed over the substrate; electrically conductive wires formed in the dielectric layer, the wires interconnecting semiconductor devices formed in the substrate into circuits; and an alpha particle emitting region in the integrated circuit chip proximate to one or more of the semiconductor devices. The method includes exposing the integrated circuit to an artificial flux of thermal neutrons to cause fission of atoms in the alpha particle emitting region into alpha particles and other atoms.
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