发明申请
- 专利标题: Back-Off Timing Mechanism
- 专利标题(中): 后退时机机制
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申请号: US11853898申请日: 2007-09-12
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公开(公告)号: US20090070507A1公开(公告)日: 2009-03-12
- 发明人: Shigehiro Asano , Tsutomu Ishii
- 申请人: Shigehiro Asano , Tsutomu Ishii
- 主分类号: G06F13/00
- IPC分类号: G06F13/00
摘要:
Systems and methods for implementing back-off timing for retries of commands sent from a master device to a slave device over a split-transaction bus. One embodiment includes a buffer having entries for storing each pending command and associated information, including a number of retries of the command and a static pseudorandom timer expiration value. The timer expiration value of each entry is compared to a running counter according to a mask associated with the number of retries of the command corresponding to the entry. When the unmasked bits of the two values match, the command is retried. In one embodiment, the same portion of the buffer entry that is used to store the number of retries and the timer expiration value is alternately used to store a slave-generated tag that is received with an acknowledgment response.
公开/授权文献
- US07613859B2 Back-off timing mechanism in a digital signal processor 公开/授权日:2009-11-03
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