发明申请
- 专利标题: METHOD OF PROCESSING SEMICONDUCTOR WAFER
- 专利标题(中): 加工半导体波形的方法
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申请号: US12199547申请日: 2008-08-27
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公开(公告)号: US20090075461A1公开(公告)日: 2009-03-19
- 发明人: Hiroyasu ISHIDA , Yasuyuki Sayama
- 申请人: Hiroyasu ISHIDA , Yasuyuki Sayama
- 申请人地址: JP Moriguchi-shi JP Ora-gun
- 专利权人: SANYO ELECTRIC CO., LTD.,SANYO SEMICONDUCTOR CO., LTD.
- 当前专利权人: SANYO ELECTRIC CO., LTD.,SANYO SEMICONDUCTOR CO., LTD.
- 当前专利权人地址: JP Moriguchi-shi JP Ora-gun
- 优先权: JP2007-238290 20070913
- 主分类号: H01L21/20
- IPC分类号: H01L21/20 ; H01L21/311
摘要:
Formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed on the semiconductor substrate for at least three times to form all semiconductor layers, of the epitaxial layers. Thereby, impurity concentration profiles of the semiconductor layers can be uniform, and pn junctions can be formed vertically to a wafer surface. Furthermore, the semiconductor layers can each be formed with a narrow width, so that impurity concentrations thereof are increased. With this configuration, high breakdown voltage and low resistance can be achieved.
公开/授权文献
- US07902053B2 Method of processing semiconductor wafer 公开/授权日:2011-03-08
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