发明申请
US20090085185A1 STACK-TYPE SEMICONDUCTOR PACKAGE, METHOD OF FORMING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME
审中-公开
堆叠型半导体封装,其形成方法和包括其的电子系统
- 专利标题: STACK-TYPE SEMICONDUCTOR PACKAGE, METHOD OF FORMING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME
- 专利标题(中): 堆叠型半导体封装,其形成方法和包括其的电子系统
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申请号: US12238781申请日: 2008-09-26
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公开(公告)号: US20090085185A1公开(公告)日: 2009-04-02
- 发明人: Hak-Kyoon BYUN , Tae-Hun KIM , Sang-Uk HAN , Jung-Do LEE , Seon-Hyang YOU
- 申请人: Hak-Kyoon BYUN , Tae-Hun KIM , Sang-Uk HAN , Jung-Do LEE , Seon-Hyang YOU
- 申请人地址: KR Gyeonggi-do
- 专利权人: SAMSUNG ELECTRONICS CO., LTD.
- 当前专利权人: SAMSUNG ELECTRONICS CO., LTD.
- 当前专利权人地址: KR Gyeonggi-do
- 优先权: KR2007-0098705 20071001
- 主分类号: H01L23/538
- IPC分类号: H01L23/538
摘要:
A stack-type semiconductor package, a method of forming the same, and an electronic system including the same are provided. The stack-type semiconductor package includes: a lower printed circuit board having a plurality of connection bumps disposed on an upper surface of the lower printed circuit board and a plurality of lower interconnections; at least one first lower chip sequentially stacked on the lower printed circuit board and electrically connected to the plurality of lower interconnections; a lower molding resin compound disposed on the lower printed circuit board and covering the first lower chips; a double-sided wiring board bonded to the lower molding resin compound and electrically connected to the connection bumps; and an upper chip package bonded to the double-sided wiring board and having upper bumps electrically connected to an interconnection pattern of the double-sided wiring board.
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