公开(公告)号：US20170330862A1

公开(公告)日：2017-11-16

申请号：US15662764

申请日：2017-07-28

申请人： Yeong-Hwan CHOE ,  Tae-Joo HWANG ,  Tae-Hong MIN ,  Young-Kun JEE ,  Sang-Uk HAN

发明人： Yeong-Hwan CHOE ,  Tae-Joo HWANG ,  Tae-Hong MIN ,  Young-Kun JEE ,  Sang-Uk HAN

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/71 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/06156 ,  H01L2224/10125 ,  H01L2224/131 ,  H01L2224/14156 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75305 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/014

摘要： A semiconductor device includes at least first and second semiconductor chips stacked on each other along a first direction, at least one through-silicon-via (TSV) through at least the first semiconductor chip of the first and second semiconductor chips, a contact pad on the at least one TSV of the first semiconductor chip, the contact pad electrically connecting the TSV of the first semiconductor chip to the second semiconductor chip, and a plurality of dummy pads on the first semiconductor chip, the plurality of dummy pads being spaced apart from each other and from the contact pad along a second direction, and the dummy pads having same heights as the contact pads as measured between respective top and bottom surfaces along the first direction.

公开(公告)号：US09818732B2

公开(公告)日：2017-11-14

申请号：US14867806

申请日：2015-09-28

申请人： Jae-Min Jung ,  Sang-Uk Han ,  KwanJai Lee ,  KyongSoon Cho ,  Jeong-Kyu Ha

发明人： Jae-Min Jung ,  Sang-Uk Han ,  KwanJai Lee ,  KyongSoon Cho ,  Jeong-Kyu Ha

IPC分类号： H01L25/16 ,  H01L23/498 ,  H01L51/52 ,  H01L27/32

CPC分类号： H01L25/167 ,  H01L23/49827 ,  H01L23/4985 ,  H01L27/323 ,  H01L27/3276 ,  H01L27/3288 ,  H01L51/52 ,  H01L51/524 ,  H01L2251/5338 ,  H01L2924/0002 ,  H01L2924/00

摘要： Chip-on-film packages and device assemblies including the same may be provided. The device assembly includes a film package including a semiconductor chip, a panel substrate connected to one end of the film package, a display panel disposed on the panel substrate, and a controlling part connected to another end of the film package. The film package includes a film substrate, a first wire disposed on a top surface of the film substrate, and a second wire disposed on a bottom surface of the film substrate.

公开(公告)号：US20160013174A1

公开(公告)日：2016-01-14

申请号：US14736247

申请日：2015-06-10

申请人： Sang-Uk HAN ,  Seungwon PARK ,  Un-Byoung KANG ,  Taeje CHO

发明人： Sang-Uk HAN ,  Seungwon PARK ,  Un-Byoung KANG ,  Taeje CHO

IPC分类号： H01L25/00 ,  H01L21/82 ,  H01L23/48 ,  H01L21/56

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/82 ,  H01L23/3128 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/00

摘要： Embodiments of the inventive concepts provide a semiconductor package and a method of fabricating the same. The method includes forming a groove to separate first semiconductor chips from each other. Forming the groove include performing a first sawing process on a bottom surface of a semiconductor substrate to cut the semiconductor substrate and a portion of a mold layer in a direction inclined with respect to the bottom surface, and performing a second sawing process to cut the mold layer in a direction substantially perpendicular to the bottom surface of the semiconductor substrate. A minimum width of the groove formed in the semiconductor substrate by the first sawing process may be greater than a width of the groove formed in the mold layer by the second sawing process.

摘要翻译： 本发明构思的实施例提供一种半导体封装及其制造方法。 该方法包括形成沟槽以将第一半导体芯片彼此分开。 形成凹槽包括在半导体衬底的底表面上执行第一锯切工艺以在相对于底表面倾斜的方向上切割半导体衬底和模具层的一部分，并且执行第二锯切工艺以切割模具 层在基本上垂直于半导体衬底的底表面的方向上。 通过第一锯切工艺在半导体衬底中形成的槽的最小宽度可以大于通过第二锯切工艺在模具层中形成的槽的宽度。

公开(公告)号：US09113545B2

公开(公告)日：2015-08-18

申请号：US13604412

申请日：2012-09-05

申请人： Sang-uk Han ,  Young-shin Kwon ,  Kwan-jai Lee ,  Jae-min Jung ,  Kyong-soon Cho ,  Jeong-kyu Ha

发明人： Sang-uk Han ,  Young-shin Kwon ,  Kwan-jai Lee ,  Jae-min Jung ,  Kyong-soon Cho ,  Jeong-kyu Ha

IPC分类号： H05K1/00 ,  H05K7/00 ,  H05K1/02 ,  H05K3/32 ,  H05K1/14 ,  H05K1/18

CPC分类号： H05K7/00 ,  H05K1/028 ,  H05K1/147 ,  H05K1/189 ,  H05K3/323 ,  H05K2201/09036 ,  H05K2201/10128

摘要： A tape wiring substrate includes a base film having at least one recess in a first surface of the base film and a chip-mounting region on which a semiconductor chip is included on a second surface of the base film. A wiring pattern is formed on the second surface of the base film and is extended to an edge of the chip-mounting region. A protection film covers the wiring pattern.

摘要翻译： 带状布线基板包括在基膜的第一表面中具有至少一个凹部的基膜和在基膜的第二表面上包含半导体芯片的芯片安装区域。 在基膜的第二表面上形成布线图案并延伸到芯片安装区域的边缘。 保护膜覆盖布线图案。

公开(公告)号：US08184449B2

公开(公告)日：2012-05-22

申请号：US12206355

申请日：2008-09-08

申请人： Jung-Do Lee ,  Hak-Kyoon Byun ,  Tae-Hun Kim ,  Sang-Uk Han ,  Seon-Hyang You

发明人： Jung-Do Lee ,  Hak-Kyoon Byun ,  Tae-Hun Kim ,  Sang-Uk Han ,  Seon-Hyang You

IPC分类号： H05K7/10 ,  H05K7/12

CPC分类号： H01L25/50 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/181 ,  Y10T29/49169 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electronic device includes a lower electronic part including a lower substrate, a lower chip structure disposed on the lower substrate, and a lower molding layer covering the lower chip structure and having a recessed region in an upper surface of the lower molding layer, and an upper electronic part including an upper substrate disposed on the lower electronic part, and an upper chip structure projecting from the upper substrate, wherein the recessed region of the lower molding layer receives the upper chip structure.

摘要翻译： 电子设备包括下电子部件，其包括下基板，设置在下基板上的下芯片结构，以及覆盖下芯片结构的下成型层，并且在下成型层的上表面具有凹部， 上部电子部件，其包括设置在下部电子部件上的上部基板和从上部基板突出的上部芯片结构，其中下部成型层的凹部区域接收上部芯片结构。

公开(公告)号：US20160064357A1

公开(公告)日：2016-03-03

申请号：US14825403

申请日：2015-08-13

申请人： Yeong-Hwan CHOE ,  Tae-Joo HWANG ,  Tae-Hong MIN ,  Young-Kun JEE ,  Sang-Uk HAN

发明人： Yeong-Hwan CHOE ,  Tae-Joo HWANG ,  Tae-Hong MIN ,  Young-Kun JEE ,  Sang-Uk HAN

IPC分类号： H01L25/065 ,  H01L23/48 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/71 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/06156 ,  H01L2224/10125 ,  H01L2224/131 ,  H01L2224/14156 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75305 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/014

摘要： A semiconductor device includes at least first and second semiconductor chips stacked on each other along a first direction, at least one silicon-through-via (TSV) through at least the first semiconductor chip of the first and second semiconductor chips, a contact pad on the at least one TSV of the first semiconductor chip, the contact pad electrically connecting the TSV of the first semiconductor chip to the second semiconductor chip, and a plurality of dummy pads on the first semiconductor chip, the plurality of dummy pads being spaced apart from each other and from the contact pad along a second direction, and the dummy pads having same heights as the contact pads as measured between respective top and bottom surfaces along the first direction.

摘要翻译： 半导体器件至少包括沿着第一方向彼此堆叠的第一和第二半导体芯片，至少一个硅通孔（TSV），至少通过第一和第二半导体芯片的第一半导体芯片，接触焊盘 所述第一半导体芯片的所述至少一个TSV，所述接触焊盘将所述第一半导体芯片的TSV电连接到所述第二半导体芯片，以及所述第一半导体芯片上的多个虚拟焊盘，所述多个虚拟焊盘与所述第一半导体芯片间隔开 彼此并且沿着第二方向从接触焊盘接合，并且虚拟焊盘具有与沿着第一方向在相应的顶部和底部表面之间测量的接触焊盘相同的高度。

公开(公告)号：US20120021600A1

公开(公告)日：2012-01-26

申请号：US13184810

申请日：2011-07-18

申请人： Sang-Uk Han ,  Dae-Woo Son ,  Kwan-Jai Lee ,  Ye-Chung Chung ,  Jeong-Kyu Ha ,  Yun-Young Kim

发明人： Sang-Uk Han ,  Dae-Woo Son ,  Kwan-Jai Lee ,  Ye-Chung Chung ,  Jeong-Kyu Ha ,  Yun-Young Kim

IPC分类号： H01L21/283

CPC分类号： H01L23/4985 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a film circuit substrate and a method of fabricating a chip package. The method of fabricating a film circuit substrate can include providing a base film including a chip packaging area to package a chip and a separation area to separate the two chip packaging areas from each other, the separation area including a cut area and an uncut area; forming a reserve interconnection pattern having a first height on the base film; and forming an interconnection pattern having a second height that is lower than the first height on the out area by selectively etching the reserve interconnection pattern of the cut area.

摘要翻译： 薄膜电路基板的制造方法以及芯片封装的制造方法。 制造薄膜电路基板的方法可以包括提供包括芯片封装区域以包装芯片的基膜和分离区域，以将两个芯片封装区域彼此分离，分离区域包括切割区域和未切割区域; 在基膜上形成具有第一高度的保留互连图案; 以及通过选择性地蚀刻所述切割区域的预留互连图案，形成具有低于所述外部区域上的所述第一高度的第二高度的互连图案。

公开(公告)号：US20090085185A1

公开(公告)日：2009-04-02

申请号：US12238781

申请日：2008-09-26

申请人： Hak-Kyoon BYUN ,  Tae-Hun KIM ,  Sang-Uk HAN ,  Jung-Do LEE ,  Seon-Hyang YOU

发明人： Hak-Kyoon BYUN ,  Tae-Hun KIM ,  Sang-Uk HAN ,  Jung-Do LEE ,  Seon-Hyang YOU

IPC分类号： H01L23/538

CPC分类号： H01L25/105 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A stack-type semiconductor package, a method of forming the same, and an electronic system including the same are provided. The stack-type semiconductor package includes: a lower printed circuit board having a plurality of connection bumps disposed on an upper surface of the lower printed circuit board and a plurality of lower interconnections; at least one first lower chip sequentially stacked on the lower printed circuit board and electrically connected to the plurality of lower interconnections; a lower molding resin compound disposed on the lower printed circuit board and covering the first lower chips; a double-sided wiring board bonded to the lower molding resin compound and electrically connected to the connection bumps; and an upper chip package bonded to the double-sided wiring board and having upper bumps electrically connected to an interconnection pattern of the double-sided wiring board.

摘要翻译： 提供堆叠型半导体封装，其形成方法和包括该堆叠型半导体封装的电子系统。 堆叠型半导体封装包括：下印刷电路板，其具有设置在下印刷电路板的上表面上的多个连接凸块和多个下互连; 至少一个第一下部芯片，其顺序地堆叠在所述下部印刷电路板上并电连接到所述多个下部互连; 设置在下部印刷电路板上并覆盖第一下部芯片的下部成型树脂组合物; 与下模塑树脂复合物接合并与连接凸块电连接的双面布线板; 以及上芯片封装，其结合到所述双面布线板并且具有电连接到所述双面布线板的布线图案的上凸块。

公开(公告)号：US20080111224A1

公开(公告)日：2008-05-15

申请号：US11790962

申请日：2007-04-30

申请人： Hak-kyoon Byun ,  Tae-je Cho ,  Jong-bo Shim ,  Sang-uk Han

发明人： Hak-kyoon Byun ,  Tae-je Cho ,  Jong-bo Shim ,  Sang-uk Han

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L23/3128 ,  H01L23/12 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Embodiments of the present invention provide a MSP having an upper and lower package, with a recess opening in the substrate of the upper package. The upper package may also include multiple stacked semiconductor chips. A lower package may include a substrate and at least one semiconductor chip. During assembly, portions of a lower package are placed into the recess opening in the substrate of the upper package. The beneficial result is a two-package MSP assembly with a reduced total height. In addition, the size and pitch of solder balls or other joints between the upper package substrate and the lower package substrate may also be reduced.

摘要翻译： 本发明的实施例提供了具有上和下封装的MSP，在上封装的基板中具有凹口。 上封装还可以包括多个堆叠的半导体芯片。 下封装可以包括基板和至少一个半导体芯片。 在组装期间，下部包装的部分被放置在上部包装的基底中的凹部开口中。 有利的结果是具有降低的总高度的双封装MSP组件。 此外，也可以减小上封装基板和下封装基板之间的焊球或其他接头的尺寸和间距。

公开(公告)号：US20160111299A1

公开(公告)日：2016-04-21

申请号：US14967490

申请日：2015-12-14

申请人： Jeong-Kyu HA ,  Youngshin KWON ,  KwanJai LEE ,  Jae-Min JUNG ,  KyongSoon CHO ,  Sang-Uk HAN

发明人： Jeong-Kyu HA ,  Youngshin KWON ,  KwanJai LEE ,  Jae-Min JUNG ,  KyongSoon CHO ,  Sang-Uk HAN

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L21/78

CPC分类号： H01L21/486 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/78 ,  H01L23/145 ,  H01L23/49524 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/50 ,  H01L2924/12042 ,  H05K1/114 ,  H05K1/115 ,  H05K1/189 ,  H05K3/0052 ,  H05K3/107 ,  H05K3/42 ,  H05K2203/1545 ,  Y10T156/1052 ,  H01L2924/00

摘要： A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern.

摘要翻译： 提供包括绝缘图案的胶带包装; 绝缘图案中的通孔中的通孔接触; 从所述通孔接触延伸到所述绝缘图案的切割表面的第一互连图案; 以及连接到绝缘图案下方的通孔接点的第二互连图案。 第二互连图案平行于第一互连图案并与绝缘图案的切割表面间隔开。