发明申请
- 专利标题: Integrated circuit and method of forming an integrated circuit
- 专利标题(中): 集成电路和形成集成电路的方法
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申请号: US11904783申请日: 2007-09-28
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公开(公告)号: US20090086523A1公开(公告)日: 2009-04-02
- 发明人: Jessica Hartwich , Lars Dreeskornfeld
- 申请人: Jessica Hartwich , Lars Dreeskornfeld
- 主分类号: G11C5/06
- IPC分类号: G11C5/06 ; H01L21/336
摘要:
An integrated circuit comprises a memory cell array portion and a support circuitry portion. The memory cell array portion comprises at least one bitline and at least one wordline, which is disposed above the bitline. The support circuitry portion comprises a FinFET comprising a gate electrode. An upper side of a portion of the gate electrode is disposed at the same height as an upper side of a portion of the bitline. A method of manufacturing an integrated circuit comprises the steps of forming a memory cell array and forming a support circuitry. The step of forming the memory cell array comprises forming a bitline and forming a wordline disposed above the bitline. The step of forming the support circuitry comprises forming a FinFET. The step of forming the FinFET comprises forming a gate electrode, an upper side of a portion of the gate electrode being formed at the same height as an upper side of a portion of the bitline.