发明申请
US20090091383A1 GAIN AMPLIFIER HAVING SWITCHED-CAPACITOR STRUCTURE FOR MINIMIZING SETTLING TIME
失效
具有开关电容结构的增益放大器,用于最小化设定时间
- 专利标题: GAIN AMPLIFIER HAVING SWITCHED-CAPACITOR STRUCTURE FOR MINIMIZING SETTLING TIME
- 专利标题(中): 具有开关电容结构的增益放大器,用于最小化设定时间
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申请号: US12195202申请日: 2008-08-20
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公开(公告)号: US20090091383A1公开(公告)日: 2009-04-09
- 发明人: Young Deuk Jeon , Young Kyun Cho , Kwi Dong Kim , Jong Kee Kwon , Jong Dae Kim
- 申请人: Young Deuk Jeon , Young Kyun Cho , Kwi Dong Kim , Jong Kee Kwon , Jong Dae Kim
- 申请人地址: KR Daejeon
- 专利权人: Electronics and Telecommunications Research Institute
- 当前专利权人: Electronics and Telecommunications Research Institute
- 当前专利权人地址: KR Daejeon
- 优先权: KR2007-100004 20071004
- 主分类号: H03F1/00
- IPC分类号: H03F1/00
摘要:
Provided is a gain amplifier having a switched-capacitor structure capable of minimizing settling time, in which an input capacitor is connected to an input terminal during a first clock sampling an input signal, and thus an output terminal of the amplifier is reset in advance to an estimated output voltage value rather than 0 by the input capacitor. Accordingly, the slight move of the output terminal of the amplifier is sufficient to settle to a desired value in an amplification mode, so that slewing time can be reduced, and as a result, overall settling time and power consumption can be minimized.
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