Successive approximation register analog-to-digital converter and operation method thereof
    1.
    发明授权
    Successive approximation register analog-to-digital converter and operation method thereof 失效
    逐次逼近寄存器模数转换器及其操作方法

    公开(公告)号:US08659463B2

    公开(公告)日:2014-02-25

    申请号:US13531418

    申请日:2012-06-22

    IPC分类号: H03M1/34

    CPC分类号: H03M1/462 H03M1/468

    摘要: Provided are a successive approximation register analog-to-digital converter and an operation method thereof. The method includes latching input signals which respectively correspond to bits of a first series of bits as digital data by directly transmitting the input signals to a latch; latching input signals which respectively correspond to bits of a second series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a first period of amplification by using a preamplifier; and latching input signals which respectively correspond to bits of a third series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a second period of amplification by using the preamplifier.

    摘要翻译: 提供了逐次逼近寄存器模数转换器及其操作方法。 该方法包括通过将输入信号直接发送到锁存器来将分别对应于第一位数位的输入信号锁定为数字数据; 通过使用前置放大器在放大的第一周期期间放大输入信号之后,通过将输入信号发送到锁存器来将分别对应于第二位数位的输入信号锁存为数字数据; 以及通过使用前置放大器在放大的第二周期期间放大输入信号之后,通过将输入信号发送到锁存器来将分别对应于第三比特位的输入信号锁存为数字数据。

    Triangular wave generator and method generating triangular wave thereof
    2.
    发明授权
    Triangular wave generator and method generating triangular wave thereof 有权
    三角波发生器及其三角波产生方法

    公开(公告)号:US08604845B2

    公开(公告)日:2013-12-10

    申请号:US13488337

    申请日:2012-06-04

    IPC分类号: H03K4/06

    CPC分类号: H03K4/501

    摘要: Disclosed is a triangular wave generator which includes a square wave signal generating unit configured to output a first signal transitioning to a high level from a low level via an output terminal in response to a first transition of a clock signal and to transition the first signal to a low level from a high level in response to a reset signal; a resistance unit configured to adjust a voltage level of a the square wave signal; and a capacitance unit configured to receive an output signal of the resistance unit to generate a second signal rising to a high level from a low level with a slope, to provide the reset signal to the square wave signal generating unit, and to output a triangular signal by falling the second signal to a low level from a high level with a slope.

    摘要翻译: 公开了一种三角波发生器,其包括方波信号生成单元,其被配置为响应于时钟信号的第一转换,经由输出端子输出从低电平转换到高电平的第一信号,并且将第一信号转换为 响应于复位信号从高电平的低电平; 电阻单元,被配置为调整所述方波信号的电压电平; 以及电容单元,被配置为接收电阻单元的输出信号,以产生从具有斜率的低电平上升到高电平的第二信号,以将复位信号提供给方波信号生成单元,并输出三角形 通过从具有斜率的高电平将第二信号降低到低电平来产生信号。

    SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND OPERATION METHOD THEREOF
    3.
    发明申请
    SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND OPERATION METHOD THEREOF 失效
    后续逼近寄存器模拟数字转换器及其操作方法

    公开(公告)号:US20130135126A1

    公开(公告)日:2013-05-30

    申请号:US13531418

    申请日:2012-06-22

    IPC分类号: H03M1/38

    CPC分类号: H03M1/462 H03M1/468

    摘要: Provided are a successive approximation register analog-to-digital converter and an operation method thereof. The method includes latching input signals which respectively correspond to bits of a first series of bits as digital data by directly transmitting the input signals to a latch; latching input signals which respectively correspond to bits of a second series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a first period of amplification by using a preamplifier; and latching input signals which respectively correspond to bits of a third series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a second period of amplification by using the preamplifier.

    摘要翻译: 提供了逐次逼近寄存器模数转换器及其操作方法。 该方法包括通过将输入信号直接发送到锁存器来将分别对应于第一位数位的输入信号锁定为数字数据; 通过使用前置放大器在放大的第一周期期间放大输入信号之后,通过将输入信号发送到锁存器来将分别对应于第二位数位的输入信号锁存为数字数据; 以及通过使用前置放大器在放大的第二周期期间放大输入信号之后,通过将输入信号发送到锁存器来将分别对应于第三比特位的输入信号锁存为数字数据。

    Multi-stage successive approximation register analog-to-digital converter and analog-to-digital converting method using the same
    4.
    发明授权
    Multi-stage successive approximation register analog-to-digital converter and analog-to-digital converting method using the same 有权
    多级逐次逼近寄存器模数转换器和使用其的模数转换方法

    公开(公告)号:US07999719B2

    公开(公告)日:2011-08-16

    申请号:US12433764

    申请日:2009-04-30

    IPC分类号: H03M1/38

    CPC分类号: H03M1/164 H03M1/468

    摘要: A multi-stage Successive Approximation Register Analog-to-Digital Converter (SAR ADC) and an analog-to-digital converting method using the same are provided. The multi-stage SAR ADC connects small-size and low-power SAR ADCs in multiple stages, thereby reducing a whole chip size and power consumption. The analog-to-digital converting method simultaneously performs analog-to-digital conversions in the SAR ADCs connected in the multiple stages, thereby reducing an analog-to-digital conversion time and maintaining an operating rate of several tens of MHz to several hundreds of MHz similar to that of a pipeline ADC.

    摘要翻译: 提供了多级连续近似寄存器模数转换器(SAR ADC)和使用其的模数转换方法。 多级SAR ADC多级连接小尺寸和低功耗SAR ADC,从而降低整个芯片尺寸和功耗。 模数转换方法同时在多级连接的SAR ADC中执行模数转换,从而减少模数转换时间,并将几十MHz至几百 MHz与流水线ADC类似。

    REFERENCE VOLTAGE SUPPLY CIRCUIT
    5.
    发明申请
    REFERENCE VOLTAGE SUPPLY CIRCUIT 有权
    参考电压供电电路

    公开(公告)号:US20110018629A1

    公开(公告)日:2011-01-27

    申请号:US12833841

    申请日:2010-07-09

    IPC分类号: H03F3/68

    CPC分类号: H03F3/347

    摘要: A reference voltage supply circuit is provided. The reference voltage supply circuit includes a first amplifier for amplifying a first input voltage and a fed back first reference voltage, a second amplifier for amplifying a second input voltage and a fed back second reference voltage, a reference voltage generator for generating the first reference voltage and the second reference voltage according to output signals of the first and second amplifiers and feeding the first and second reference voltages back to the first and second amplifiers, and a glitch remover turned on/off according to an input pulse signal to conduct or cut off current flowing between a power supply terminal and the ground.

    摘要翻译: 提供参考电压供应电路。 参考电压供应电路包括用于放大第一输入电压和反馈第一参考电压的第一放大器,用于放大第二输入电压的第二放大器和反馈的第二参考电压;参考电压发生器,用于产生第一参考电压 以及根据第一和第二放大器的输出信号的第二参考电压,并将第一和第二参考电压馈送回第一和第二放大器,并且毛刺去除器根据输入脉冲信号导通/截止以导通或切断 在电源端子和地之间流动的电流。

    HIGH-SPEED MULTI-STAGE VOLTAGE COMPARATOR
    6.
    发明申请
    HIGH-SPEED MULTI-STAGE VOLTAGE COMPARATOR 失效
    高速多级电压比较器

    公开(公告)号:US20100156469A1

    公开(公告)日:2010-06-24

    申请号:US12507357

    申请日:2009-07-22

    IPC分类号: H03F3/45

    摘要: A high-speed multi-stage voltage comparator is provided. The multi-stage voltage comparator is configured to eliminate offset from outputs of preamplifiers through respective offset-cancellation switches, and to reset the outputs of the preamplifiers through respective reset switches to reduce an output recovery time. Thus, the multi-stage voltage comparator operates with high accuracy and at a high speed, so that it can be usefully applied to an analog-to-digital converter (ADC), and particularly, a high-speed successive approximation register ADC (SAR ADC).

    摘要翻译: 提供了一个高速多级电压比较器。 多级电压比较器被配置为消除通过相应的偏移消除开关的前置放大器的输出的偏移,并且通过相应的复位开关复位前置放大器的输出以减少输出恢复时间。 因此,多级电压比较器以高精度和高速运行,从而可以有效地应用于模数转换器(ADC),特别是高速逐次逼近寄存器ADC(SAR) ADC)。

    MULTI-STAGE SUCCESSIVE APPROXIMATION REGISTER ANALOG-TODIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERTING METHOD USING THE SAME
    7.
    发明申请
    MULTI-STAGE SUCCESSIVE APPROXIMATION REGISTER ANALOG-TODIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERTING METHOD USING THE SAME 有权
    多级连续逼近寄存器模拟转换器和使用该模拟转换器的模拟数字转换方法

    公开(公告)号:US20100066583A1

    公开(公告)日:2010-03-18

    申请号:US12433764

    申请日:2009-04-30

    IPC分类号: H03M1/38

    CPC分类号: H03M1/164 H03M1/468

    摘要: A multi-stage Successive Approximation Register Analog-to-Digital Converter (SAR ADC) and an analog-to-digital converting method using the same are provided. The multi-stage SAR ADC connects small-size and low-power SAR ADCs in multiple stages, thereby reducing a whole chip size and power consumption. The analog-to-digital converting method simultaneously performs analog-to-digital conversions in the SAR ADCs connected in the multiple stages, thereby reducing an analog-to-digital conversion time and maintaining an operating rate of several tens of MHz to several hundreds of MHz similar to that of a pipeline ADC.

    摘要翻译: 提供了多级连续近似寄存器模数转换器(SAR ADC)和使用其的模数转换方法。 多级SAR ADC多级连接小尺寸和低功耗SAR ADC,从而降低整个芯片尺寸和功耗。 模数转换方法同时在多级连接的SAR ADC中执行模数转换,从而减少模数转换时间,并将几十MHz至几百 MHz与流水线ADC类似。

    BAND-GAP REFERENCE VOLTAGE GENERATOR
    8.
    发明申请
    BAND-GAP REFERENCE VOLTAGE GENERATOR 有权
    带隙参考电压发生器

    公开(公告)号:US20100052643A1

    公开(公告)日:2010-03-04

    申请号:US12428425

    申请日:2009-04-22

    IPC分类号: G05F3/16

    CPC分类号: G05F3/30

    摘要: A band-gap reference voltage generator is provided. N-channel metal oxide semiconductor (NMOS) transistors are respectively connected to bipolar transistors in parallel. A Complementary To Absolute Temperature (CTAT) voltage that is inversely proportional to absolute temperature is reduced by a threshold voltage of the NMOS transistor. A weight for a temperature coefficient of a Proportional To Absolute Temperature (PTAT) voltage that is directly proportional to absolute temperature is reduced and a resistance ratio for a temperature coefficient of 0 is reduced by about ½, thereby miniaturizing the band-gap reference voltage generator. A reference voltage lower than or equal to 1 V can be provided by resistors respectively connected to the bipolar transistors in parallel.

    摘要翻译: 提供带隙参考电压发生器。 N沟道金属氧化物半导体(NMOS)晶体管分别并联连接到双极晶体管。 与绝对温度成反比的绝对温度互补(CTAT)电压降低了NMOS晶体管的阈值电压。 与绝对温度成正比的比例绝对温度(PTAT)电压的温度系数的重量减小,温度系数为0的电阻比减小约1/2,从而使带隙基准电压发生器 。 可以通过并联连接到双极晶体管的电阻器提供低于或等于1V的参考电压。

    High voltage MOSFET having Si/SiGe heterojuction structure and method of manufacturing the same
    9.
    发明授权
    High voltage MOSFET having Si/SiGe heterojuction structure and method of manufacturing the same 有权
    具有Si / SiGe异质结构的高压MOSFET及其制造方法

    公开(公告)号:US07233018B2

    公开(公告)日:2007-06-19

    申请号:US11182671

    申请日:2005-07-15

    IPC分类号: H01L29/06 H01L31/00

    摘要: Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced.

    摘要翻译: 提供了具有Si / SiGe异质结结构的高压金属氧化物半导体场效应晶体管(HVMOSFET)及其制造方法。 在该方法中,层叠有Si层,弛豫SiGe外延层,SiGe外延层和Si外延层的基板或其上具有阱区的Si层,SiGe外延层和 Si外延层被形成。 对于具有异质结结构的器件,通过势阱的导电载流子数量和载流子的迁移率增加,以降低导通电阻,从而增加饱和电流。 此外,垂直电场的强度降低,使得击穿电压可以保持在非常高的水平。 此外,由于异质结构造成的垂直电场的减小导致跨导(Gm)的增益,结果是热电子效应被抑制,并且器件的可靠性增强。

    DLL circuit having two input standard clocks, clock signal generation circuit having the DLL circuit and clock signal generation method
    10.
    发明申请
    DLL circuit having two input standard clocks, clock signal generation circuit having the DLL circuit and clock signal generation method 审中-公开
    具有两个输入标准时钟的DLL电路,具有DLL电路和时钟信号产生方法的时钟信号产生电路

    公开(公告)号:US20070086555A1

    公开(公告)日:2007-04-19

    申请号:US11429350

    申请日:2006-05-05

    申请人: Young-Kyun Cho

    发明人: Young-Kyun Cho

    IPC分类号: H03D3/24

    摘要: Provided is a delay locked loop circuit having two input standard clocks, a clock signal generation circuit including a delay locked loop circuit and a clock signal generation method. The delay locked loop circuit of the present invention includes a delay line unit, a phase comparator and a delay control unit. The delay line unit receives the first standard clock and generates an internal clock by delaying the first standard clock in response to a control signal. The phase comparator compares a phase difference between the first standard clock and a second standard clock with a phase difference between the first standard clock and the internal clock. The delay control unit generates a control signal to control a phase of the internal clock based on a comparison result of the phase comparator. According to the present invention, the clock signal having any phase shift may be simply generated by controlling the phase between an input and an output clock of the DLL based on the phase between two standard clocks and a layout size and a power consumption are greatly reduced.

    摘要翻译: 提供了具有两个输入标准时钟的延迟锁定环电路,包括延迟锁定环电路和时钟信号产生方法的时钟信号产生电路。 本发明的延迟锁定环电路包括延迟线单元,相位比较器和延迟控制单元。 延迟线单元接收第一标准时钟并通过响应于控制信号延迟第一标准时钟来产生内部时钟。 相位比较器将第一标准时钟和第二标准时钟之间的相位差与第一标准时钟和内部时钟之间的相位差进行比较。 延迟控制单元根据相位比较器的比较结果生成控制内部时钟的相位的控制信号。 根据本发明,具有任何相移的时钟信号可以简单地通过基于两个标准时钟之间的相位和布局尺寸来控制DLL的输入和输出时钟之间的相位而大大降低功耗 。