摘要:
Provided are a successive approximation register analog-to-digital converter and an operation method thereof. The method includes latching input signals which respectively correspond to bits of a first series of bits as digital data by directly transmitting the input signals to a latch; latching input signals which respectively correspond to bits of a second series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a first period of amplification by using a preamplifier; and latching input signals which respectively correspond to bits of a third series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a second period of amplification by using the preamplifier.
摘要:
Disclosed is a triangular wave generator which includes a square wave signal generating unit configured to output a first signal transitioning to a high level from a low level via an output terminal in response to a first transition of a clock signal and to transition the first signal to a low level from a high level in response to a reset signal; a resistance unit configured to adjust a voltage level of a the square wave signal; and a capacitance unit configured to receive an output signal of the resistance unit to generate a second signal rising to a high level from a low level with a slope, to provide the reset signal to the square wave signal generating unit, and to output a triangular signal by falling the second signal to a low level from a high level with a slope.
摘要:
Provided are a successive approximation register analog-to-digital converter and an operation method thereof. The method includes latching input signals which respectively correspond to bits of a first series of bits as digital data by directly transmitting the input signals to a latch; latching input signals which respectively correspond to bits of a second series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a first period of amplification by using a preamplifier; and latching input signals which respectively correspond to bits of a third series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a second period of amplification by using the preamplifier.
摘要:
A multi-stage Successive Approximation Register Analog-to-Digital Converter (SAR ADC) and an analog-to-digital converting method using the same are provided. The multi-stage SAR ADC connects small-size and low-power SAR ADCs in multiple stages, thereby reducing a whole chip size and power consumption. The analog-to-digital converting method simultaneously performs analog-to-digital conversions in the SAR ADCs connected in the multiple stages, thereby reducing an analog-to-digital conversion time and maintaining an operating rate of several tens of MHz to several hundreds of MHz similar to that of a pipeline ADC.
摘要:
A reference voltage supply circuit is provided. The reference voltage supply circuit includes a first amplifier for amplifying a first input voltage and a fed back first reference voltage, a second amplifier for amplifying a second input voltage and a fed back second reference voltage, a reference voltage generator for generating the first reference voltage and the second reference voltage according to output signals of the first and second amplifiers and feeding the first and second reference voltages back to the first and second amplifiers, and a glitch remover turned on/off according to an input pulse signal to conduct or cut off current flowing between a power supply terminal and the ground.
摘要:
A high-speed multi-stage voltage comparator is provided. The multi-stage voltage comparator is configured to eliminate offset from outputs of preamplifiers through respective offset-cancellation switches, and to reset the outputs of the preamplifiers through respective reset switches to reduce an output recovery time. Thus, the multi-stage voltage comparator operates with high accuracy and at a high speed, so that it can be usefully applied to an analog-to-digital converter (ADC), and particularly, a high-speed successive approximation register ADC (SAR ADC).
摘要:
A multi-stage Successive Approximation Register Analog-to-Digital Converter (SAR ADC) and an analog-to-digital converting method using the same are provided. The multi-stage SAR ADC connects small-size and low-power SAR ADCs in multiple stages, thereby reducing a whole chip size and power consumption. The analog-to-digital converting method simultaneously performs analog-to-digital conversions in the SAR ADCs connected in the multiple stages, thereby reducing an analog-to-digital conversion time and maintaining an operating rate of several tens of MHz to several hundreds of MHz similar to that of a pipeline ADC.
摘要:
A band-gap reference voltage generator is provided. N-channel metal oxide semiconductor (NMOS) transistors are respectively connected to bipolar transistors in parallel. A Complementary To Absolute Temperature (CTAT) voltage that is inversely proportional to absolute temperature is reduced by a threshold voltage of the NMOS transistor. A weight for a temperature coefficient of a Proportional To Absolute Temperature (PTAT) voltage that is directly proportional to absolute temperature is reduced and a resistance ratio for a temperature coefficient of 0 is reduced by about ½, thereby miniaturizing the band-gap reference voltage generator. A reference voltage lower than or equal to 1 V can be provided by resistors respectively connected to the bipolar transistors in parallel.
摘要:
Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced.
摘要:
Provided is a delay locked loop circuit having two input standard clocks, a clock signal generation circuit including a delay locked loop circuit and a clock signal generation method. The delay locked loop circuit of the present invention includes a delay line unit, a phase comparator and a delay control unit. The delay line unit receives the first standard clock and generates an internal clock by delaying the first standard clock in response to a control signal. The phase comparator compares a phase difference between the first standard clock and a second standard clock with a phase difference between the first standard clock and the internal clock. The delay control unit generates a control signal to control a phase of the internal clock based on a comparison result of the phase comparator. According to the present invention, the clock signal having any phase shift may be simply generated by controlling the phase between an input and an output clock of the DLL based on the phase between two standard clocks and a layout size and a power consumption are greatly reduced.