发明申请
US20090119355A1 ARITHMETIC LOGICAL UNIT, COMPUTATION METHOD AND COMPUTER SYSTEM 失效
算术逻辑单元,计算方法和计算机系统

  • 专利标题: ARITHMETIC LOGICAL UNIT, COMPUTATION METHOD AND COMPUTER SYSTEM
  • 专利标题(中): 算术逻辑单元,计算方法和计算机系统
  • 申请号: US12025891
    申请日: 2008-02-05
  • 公开(公告)号: US20090119355A1
    公开(公告)日: 2009-05-07
  • 发明人: Hiroshi NAKAGOEYasushi Nagai
  • 申请人: Hiroshi NAKAGOEYasushi Nagai
  • 申请人地址: JP Tokyo
  • 专利权人: Hitachi, Ltd.
  • 当前专利权人: Hitachi, Ltd.
  • 当前专利权人地址: JP Tokyo
  • 优先权: JP2007-285520 20071101
  • 主分类号: G06F7/00
  • IPC分类号: G06F7/00
ARITHMETIC LOGICAL UNIT, COMPUTATION METHOD AND COMPUTER SYSTEM
摘要:
This arithmetic logical unit outputs data to be used in checking the final result of an AES unit that encrypts a plain text block into an encrypted text block based on AES operation, and includes an arithmetic unit for computing parity data created based on XOR operation from an encryption key to be used as a key during AES encryption, parity data created based on XOR operation from a plain text block, and an AES operation halfway result output from the AES unit, and outputting a value that is equivalent to parity data created based on XOR operation from the final result of the AES unit.
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