公开(公告)号：US09092288B2

公开(公告)日：2015-07-28

申请号：US13290380

申请日：2011-11-07

申请人： Yasushi Nagai ,  Atsushi Shimizu ,  Hiroyuki Kasuya ,  Shoichi Akutsu ,  Shinji Kawamura ,  Yoshitaka Sumitomo

发明人： Yasushi Nagai ,  Atsushi Shimizu ,  Hiroyuki Kasuya ,  Shoichi Akutsu ,  Shinji Kawamura ,  Yoshitaka Sumitomo

IPC分类号： G06F9/44 ,  G06F7/00 ,  G06F11/30 ,  G07C5/00 ,  G06F9/445 ,  G06F11/14 ,  G06F1/30

CPC分类号： G06F8/61 ,  G06F1/30 ,  G06F11/1433 ,  G07C5/00

摘要： When a power supply is cut off on updating programs, improper data remains since the power source to be supplied to the vehicle-mounted device is unstable. The check for the improper data and restoration processing are required for a reactivation processing implemented by an update processing unit so that the update is completed correctly, therefore, the user is waited. In contrast, the update processing also implemented by the update processing unit for a time period during which the power source becomes unstable is interrupted, and implemented for the time period during which the power source voltage is stable. The power source voltage is considered to be unstable based on a function of the vehicle speed, brake pedal actuation, parking brake actuation, and/or power source activation. In consequence, the update processing is carried on steadily without making the user wait.

摘要翻译： 当电源更新程序被切断时，由于提供给车载设备的电源不稳定，所以不正确的数据仍然存在。 对于由更新处理单元执行的重新激活处理，需要检查不正确的数据和恢复处理，使得更新被正确完成，因此等待用户。 相反，在电源变得不稳定的时间段期间，由更新处理单元也实现的更新处理被中断，并且在电源电压稳定的时间段内实现。 基于车速，制动踏板驱动，驻车制动器致动和/或电源激活的功能，电源电压被认为是不稳定的。 因此，更新处理在不使用户等待的情况下稳定地进行。

公开(公告)号：US20120331186A1

公开(公告)日：2012-12-27

申请号：US13603456

申请日：2012-09-05

申请人： Yasushi NAGAI ,  Hiroshi NAKAGOE ,  Shigeki TAIRA

发明人： Yasushi NAGAI ,  Hiroshi NAKAGOE ,  Shigeki TAIRA

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： The DMA controller includes a peripheral device read unit to read states of peripheral devices, a state comparator, a transfer unit, a register, and a peripheral device write unit to write data in the peripheral devices according to the contents in the register when the DMA transfer is executed, an interrupt select unit selects one of plural interrupt signals to determine whether the peripheral device read unit, the state comparator and the transfer unit are at a timing to execute operations. Based on these operations the state comparator determines whether to start the DMA transfer, and the transfer unit executes data transfer between the peripheral devices.

公开(公告)号：US08176221B2

公开(公告)日：2012-05-08

申请号：US12595381

申请日：2008-03-21

申请人： Yasushi Nagai ,  Hiroshi Nakagoe ,  Shigeki Taira

发明人： Yasushi Nagai ,  Hiroshi Nakagoe ,  Shigeki Taira

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： A DMA controller achieving real-time control of a DMA transfer relating to periodically operated peripheral devices at a low cost and with low power consumption. A typical embodiment of the invention is a DMA controller having: a counter for counting time; a counter comparator comparing a value of the counter and a counter value indicating an expected time of a DMA transfer; a peripheral device read unit reading a register of the peripheral device to acquire a state of a peripheral device by; and a state comparator comparing a value of the register read by the peripheral device read unit and a start condition of the DMA transfer, in which, with being triggered by establishment of a comparison result by the counter comparator, in accordance with a specified order, a processing of updating the counter value indicating the expected time of a DMA transfer to a value indicating a next expected time, a read of the register of the peripheral device by the peripheral device read unit, a comparison by the state comparator, and a DMA transfer on the condition that the comparison result by the state comparator is established are executed.

摘要翻译： DMA控制器以低成本和低功耗实现与周期性操作的外围设备相关的DMA传输的实时控制。 本发明的典型实施例是一种DMA控制器，具有：计数时间的计数器; 比较计数器的值和表示DMA传送的预期时间的计数器值的计数器比较器; 外围设备读取单元，读取外围设备的寄存器，以通过以下方式获取外围设备的状态; 以及状态比较器，比较由外围设备读取单元读取的寄存器的值和DMA传输的开始条件，其中，通过由计数器比较器建立比较结果而触发，根据指定的顺序， 将指示DMA传输的预期时间的计数器值更新为指示下一个预期时间的值的处理，外围设备读取单元对外围设备的寄存器的读取，状态比较器的比较以及DMA 在状态比较器的比较结果建立的条件下进行转移。

公开(公告)号：US07853733B2

公开(公告)日：2010-12-14

申请号：US11984432

申请日：2007-11-16

申请人： Hiroshi Nakagoe ,  Yasushi Nagai

发明人： Hiroshi Nakagoe ,  Yasushi Nagai

IPC分类号： G06F13/28

CPC分类号： H04L1/0052 ,  H04L1/0057

摘要： An operational circuit for performing an operation of an arbitrary number of input data pieces by using a DMA transfer according to a descriptor control and output results. The arbitrary number of input data pieces are divided into a plurality of pieces to perform an operation processing without performing the operation of the arbitrary number of input data pieces at a time. The operational circuit once stores an intermediate result for each of the divided operations in an external storage device, performs an operation processing read with an intermediate result in the next operation processing, and obtains a final result by repeating these operation processings. The operation is performed at a cyclic unit of processing corresponding to the number of address registers provided in the operational circuit.

摘要翻译： 一种操作电路，用于通过使用根据描述符控制和输出结果的DMA传输来执行任意数量的输入数据的操作。 任意数量的输入数据被分成多个，以执行一次操作处理，而不一次执行任意数量的输入数据的操作。 运算电路一次将分割运算的中间结果存储在外部存储装置中，进行下一个运算处理中的中间结果的运算处理，通过重复这些运算处理，得到最终结果。 该操作以对应于在操作电路中提供的地址寄存器的数量的循环处理单元进行。

公开(公告)号：US20080294913A1

公开(公告)日：2008-11-27

申请号：US12014250

申请日：2008-01-15

申请人： Hiroshi NAKAGOE ,  Toru Owada ,  Yasushi Nagai

发明人： Hiroshi NAKAGOE ,  Toru Owada ,  Yasushi Nagai

IPC分类号： H04L9/06

CPC分类号： H04L9/0637 ,  H04L2209/125

摘要： Provided is a disk array controller capable of speeding up the processing by simultaneously execution the encryption/decryption of a non parallel block cipher modes of operation. In a disk array controller for controlling a disk array according to a disk access request from a host system, a plurality of non parallel mode encryption/decryption target data are divided into a plurality of messages unrelated to the encryption/decryption processing, partitioning non parallel mode encryption/decryption target data belonging to the respective messages into a plurality of block data, storing each block data belonging to the respective messages by allocating it each line of Rnd[0] to Rnd[R−1] per message, and encrypting/decrypting block data corresponding to block data corresponding to a cell of the same column of each line among the block data stored in a data buffer simultaneously with the pipeline processing performed by a pipeline encryption/decryption circuit.

摘要翻译： 提供了一种能够通过同时执行非并行块加密操作模式的加密/解密来加速处理的盘阵列控制器。 在用于根据来自主机系统的磁盘访问请求来控制磁盘阵列的磁盘阵列控制器中，多个非并行模式加密/解密目标数据被分成与加密/解密处理无关的多个消息，分割非并行 将属于各个消息的模式加密/解密目标数据转换为多个块数据，通过将每个消息的Rnd [0]到Rnd [R-1]的每一行分配来存储属于各个消息的每个块数据，以及加密/ 在与由流水线加密/解密电路执行的流水线处理同时处理与数据缓冲器中存储的块数据中的与每行相同列的单元相对应的块数据的块数据解密。

公开(公告)号：US08275128B2

公开(公告)日：2012-09-25

申请号：US12025891

申请日：2008-02-05

申请人： Hiroshi Nakagoe ,  Yasushi Nagai

发明人： Hiroshi Nakagoe ,  Yasushi Nagai

IPC分类号： H04L29/06

CPC分类号： G11B20/00086 ,  G06F7/00 ,  G11B20/0021 ,  G11B20/1833 ,  G11B2020/1843 ,  G11B2220/2516 ,  H04L9/0631 ,  H04L2209/122 ,  H04L2209/125 ,  H04L2209/34

摘要： This arithmetic logical unit outputs data to be used in checking the final result of an AES unit that encrypts a plain text block into an encrypted text block based on AES operation, and includes an arithmetic unit for computing parity data created based on XOR operation from an encryption key to be used as a key during AES encryption, parity data created based on XOR operation from a plain text block, and an AES operation halfway result output from the AES unit, and outputting a value that is equivalent to parity data created based on XOR operation from the final result of the AES unit.

摘要翻译： 该算术逻辑单元输出用于将基于AES操作将加密文本块加密的AES单元的最终结果的数据输出到加密文本块中，并且包括用于计算从基于AES操作的异或运算创建的奇偶校验数据的运算单元 在AES加密期间用作密钥的加密密钥，基于来自纯文本块的异或操作创建的奇偶校验数据，以及AES单元输出的AES操作中途结果，并输出等价于基于 来自AES单元的最终结果的异或运算。

公开(公告)号：US20120191882A1

公开(公告)日：2012-07-26

申请号：US13437297

申请日：2012-04-02

申请人： Yasushi NAGAI ,  Hiroshi Nakagoe ,  Shigeki Taira

发明人： Yasushi NAGAI ,  Hiroshi Nakagoe ,  Shigeki Taira

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： The DMA controller includes a peripheral device read unit to read states of peripheral devices, a state comparator, a transfer unit, a register, and a peripheral device write unit to write data in the peripheral devices according to the contents in the register when the DMA transfer is executed, an interrupt select unit selects one of plural interrupt signals to determine whether the peripheral device read unit, the state comparator and the transfer unit are at a timing to execute operations. Based on these operations the state comparator determines whether to start the DMA transfer, and the transfer unit executes data transfer between the peripheral devices.

摘要翻译： DMA控制器包括外围设备读取单元，用于读取外围设备的状态，状态比较器，传送单元，寄存器和外围设备写入单元，以根据DMA中的内容在外围设备中写入数据 执行转移，中断选择单元选择多个中断信号之一来确定外围设备读取单元，状态比较器和传送单元是否处于执行操作的定时。 基于这些操作，状态比较器确定是否启动DMA传输，并且传送单元执行外围设备之间的数据传输。

公开(公告)号：US20100241771A1

公开(公告)日：2010-09-23

申请号：US12668561

申请日：2008-03-19

申请人： Yasushi Nagai ,  Hiroshi Nakagoe ,  Shigeki Taira

发明人： Yasushi Nagai ,  Hiroshi Nakagoe ,  Shigeki Taira

IPC分类号： G06F13/10 ,  G06F13/24 ,  G06F13/16

CPC分类号： G06F13/24 ,  G06F9/4806

摘要： A peripheral circuit with a host load adjusting function which is capable of readily carrying out control so that the amounts of data processed by the peripheral circuit and a host CPU are balanced by limiting interrupts made by the peripheral circuit, usage of a memory bus bandwidth, and a processing throughput of data. A typical embodiment of the present invention has an adjustment limitation setting unit setting a minimum value of an interval of interrupt requests generated by the peripheral circuit with the host load adjusting function, and a cycle counter counting generation timing of the interrupt requests, and compares a value of the cycle counter with the interval set in the adjustment limitation setting unit, thereby suppressing the interrupt requests generated at an interval shorter than the set interval.

摘要翻译： 具有主机负载调整功能的外围电路，其能够容易地执行控制，使得由外围电路和主机CPU处理的数据量通过限制外围电路所做的中断，存储器总线带宽的使用， 和数据的处理吞吐量。 本发明的典型实施例具有调整限制设置单元，其设置由主机负载调整功能产生的外围电路的中断请求的间隔的最小值，以及中断请求的周期计数器计数产生定时，并将 该值是在调整限制设定单元中设定的间隔的周期计数器的值，从而抑制以比设定间隔短的间隔生成的中断请求。

公开(公告)号：US20090265443A1

公开(公告)日：2009-10-22

申请号：US12139696

申请日：2008-06-16

申请人： Hirotaka Moribe ,  Shoji Kodama ,  Yasushi Nagai

发明人： Hirotaka Moribe ,  Shoji Kodama ,  Yasushi Nagai

IPC分类号： G06F15/16

CPC分类号： H04L12/2809 ,  G06F15/16 ,  H04L12/2807 ,  H04L12/2812 ,  H04L12/2834 ,  H04L12/2838 ,  H04L12/4625 ,  H04L67/1097

摘要： This network apparatus includes a confirmation unit for confirming an appliance connected to a network in a certain area at predetermined time intervals, a transfer unit for transferring a content retained in the appliance from the appliance connected to the network to a storage apparatus outside of the area, a setting unit for setting a virtual device of the appliance when the confirmation unit detects that the appliance has been disconnected from the network, and a distribution unit for distributing, when an acquisition request of the content is issued to the appliance disconnected from the network, the content read from the storage to a sending source of the acquisition request with the virtual device as the transmission source of the content.

摘要翻译： 该网络装置包括用于以预定的时间间隔确认连接到特定区域中的网络的设备的确认单元，用于将保存在设备中的内容从连接到网络的设备传送到区域外的存储设备的传送单元 设置单元，用于当所述确认单元检测到所述设备已经从所述网络断开连接时，设置所述设备的虚拟设备;以及分发单元，用于当将所述内容的获取请求发布到从所述网络断开连接的设备时， 将内容从存储器读取到采集请求的发送源，虚拟设备作为内容的传输源。

公开(公告)号：US20090113087A1

公开(公告)日：2009-04-30

申请号：US12263148

申请日：2008-10-31

申请人： Nobuaki Kohinata ,  Yasushi Nagai ,  Takeshi Asahi ,  Shigeki Taira ,  Keitaro Okasaki ,  Yuichi Kobayashi

发明人： Nobuaki Kohinata ,  Yasushi Nagai ,  Takeshi Asahi ,  Shigeki Taira ,  Keitaro Okasaki ,  Yuichi Kobayashi

IPC分类号： G06F3/00

CPC分类号： H04N21/4147 ,  H04N5/765 ,  H04N5/775 ,  H04N5/781 ,  H04N5/85

摘要： There are provided a stream I/F section 7 adapted to exclusively input/output stream data such as video data or audio data from/to a host section, a non-stream I/F section 5 adapted to input/output non-stream data such as an address, a command, photo data, or text data from/to the host section 3, and a recording medium I/F section 11 adapted to input/output the stream data and the non-stream data to/from a recording medium section 4, and the stream I/F section 7 is provided with transfer control means for controlling the transfer rate of the stream data in accordance with a state of use (availability) of each of a receiving buffer 6 and a transmission buffer 8 provided independently.

摘要翻译： 提供了适于独占地输入/输出诸如来自/到主机部分的视频数据或音频数据的流数据的流I / F部分7，适于输入/输出非数据流数据的非流I / F部分5 例如来自/到主机部分3的地址，命令，照片数据或文本数据，以及适于向/从记录输入/输出流数据和非流数据的记录介质I / F部分11 中间部分4和流I / F部分7设置有传送控制装置，用于根据提供的接收缓冲器6和发送缓冲器8的每个的使用状态（可用性）来控制流数据的传送速率 独立。