发明申请
- 专利标题： PLL CIRCUIT
- 专利标题（中）： PLL电路
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申请号： US12066000申请日： 2006-07-27
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公开(公告)号： US20090153203A1公开(公告)日： 2009-06-18
- 发明人: Tatsuo Okamoto , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
- 申请人： Tatsuo Okamoto , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
- 优先权： JP2005-260831 20050908
- 国际申请： PCT/JP2006/314916 WO 20060727
- 主分类号： H03L7/06
- IPC分类号： H03L7/06
摘要：
A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).
公开/授权文献
- US07746132B2 PLL circuit 公开/授权日：2010-06-29
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